AMD cuts to the core with 'Bulldozer' Opterons

[Hans de Vries]

Yes, I fully understand what he said. But during the design of an efficient (from a space/power respective) miltiplier you probably can't avoid an iterative part of multiplier tree which is hardly pipelineable.

FP Multipliers are fully pipelined since many years now...

The CRAY-1 had fully pipelined 64 bit FP multipliers in 1975
http://en.wikipedia.org/wiki/Cray-1

The Intel i860 had an on chip fully pipelined 64 bit FP multiplier in 1989
http://en.wikipedia.org/wiki/Intel_i860

Xilinx Virtex-7 family will have an FPGA with almost 4000 pipelined
multiplier blocks each with a size of 25x18 bit with which you can build
all kind of multipliers in any way you want.
http://www.xilinx.com/support/docume...s_Overview.pdf


Regards, Hans