Quote Originally Posted by JF-AMD View Post
Well, here is how I understand it. We have 2 128-bit FMACs that fuse into a 256-bit AVX. Intel "double pumps" a 128-bit unit to get it to 256-bit (I think Hans has a die shot that shows the SB 256-bit being about the same size as the current 12-bit.)

As it has been explained to me, the double pumping requires AVX, meaning that if the SW does not support AVX, then things execute at 128-bit only.

Perhaps someone with some info could chime in.
double pumping basically cuts the delay of the execution stages on half. this means double the clockspeed so whether the code uses 128bits of the avx registers or all 256bits execution will be two times faster (in theory). BD will do double operations/clock and SB will double clockspeed, two ways to solve the same problem.

i really dont think that they will use double pumping, hyperpipelining, or whatever you want to call it in sandy bridge. it caused a lot of issues in netburst. to put it simply making alu's clock 2x faster is very complex, it takes experienced designers and many circuit simulations to assure robustness. it is much more productive having these people work on other parts of the chip, like designing a really fast L1 cache, high speed I/O, or power/clock gating.