Quote Originally Posted by informal View Post
Can you be so kind then and shows us the extended FP unit on the die photo?The total die size difference is 7% and the FP unit block is just slightly different.
Well, you can always the question directly to Intel on the respective thread.

My answer : I do not know why the FPU is only 7% larger ( if we were to trust an analysis based on a low resolution photo with large margins of error ). Doubling the datapaths to 256bit causes what increase in die area ? I haven't seen an analysis on this.

Quote Originally Posted by Dresdenboy View Post
Did you check the context of the double pumping statement? For me this looks to be related to loads and the cache bandwidth/AGU resources. It's also contained in point 2). I highlighted some different parts. You can also double pump cache accesses etc.

The first version of the chart (said to be wrong in 1)) contained "AVX LO" and "AVX HI" units, also drawn at the same width as the 128 bit units. Maybe they're even not using double pumping but other techniques like wavefronts (less likely).

How would you explain the nearly unchanged area of the FPU on die? Surely not by chip stacking.
Instead of trying to find some weirdo explanations, we could take his words at face value. The words he uses are pretty straightforward :
"The chart is wrong, we will fix it. Sandy Bridge has true 256-bit FP execution units (mul, add, shuffle).
I wouldn't be surprised of some intentional misleading done previously for deceiving the competition.