AMD cuts to the core with 'Bulldozer' Opterons

[kl0012]

FP Multipliers are fully pipelined since many years now...

The CRAY-1 had fully pipelined 64 bit FP multipliers in 1975
http://en.wikipedia.org/wiki/Cray-1

The Intel i860 had an on chip fully pipelined 64 bit FP multiplier in 1989
http://en.wikipedia.org/wiki/Intel_i860

Xilinx Virtex-7 family will have an FPGA with almost 4000 pipelined
multiplier blocks each with a size of 25x18 bit with which you can build
all kind of multipliers in any way you want.
http://www.xilinx.com/support/docume...s_Overview.pdf

Regards, Hans

Thats about an actual implementation of multiplier (as I said above). You may chose parallel implementation and then you have no problem for further serializing it. But such implementation consumes much more space and power. On the other hand you may choose an iterative implementation and still get a fully pipelined multiplier if you can implement an iterative stage in one cycle but this specific stage is not pipelineable further (in case you want to rise the freq.). I know nothing about the actual implementation of multipliers in Intel's cpu, but my point is that "pipelineablilty" depends on specific design decision.