What to Expect From AMD at ISSCC 2011

[rcofell]

Like this:



Less than 9% larger than an 8 core.
A 12 core is 40% larger if you add 2 modules on a 8 core.

A 10 core is good business since it wastes less space. A 12 core don't, it's a lot harder to produce.

Nice design if photoshop is your CAD tool
However I suspect there are at least a handful of reasons why it's not such a simple matter

1. Just because those areas "look" like empty space doesn't necessarily mean they are, there's a strong chance a bit of it is synthesized logic, which hides itself well in the black & white photos. Compare the top part of the colored core to the rest of the chip to see an example (unless there's additional intentional obfuscation).

2. The photo doesn't show the interconnect/wiring track congestion at the higher levels, which could negate the ability to use such space.

3. [More nitpicky] L3 cache accesses appear to go through the crossbar (as opposed to Intel's ring bus), so who's to say how much additional wiring complexity/area would result from adding another core following the same methodology? The impact on latency would certainly be a factor too.