What to Expect From AMD at ISSCC 2011

[madcho]

the guy say jf is wrong, it's crazy, he's maybe not an engineer but he know deeply his work.

[JkS]

HMm no ...
If you mean "shared" in the sense like Bulldozer's Decoder is shared between two INT clusters, then your statement ist wrong.

These pipelines are there since the good old AMD K7 days, they consist of a pair: one AGU for adress generation and one ALU for any other, normal INT calculations.

Nothing is shared between those two pipeline. Some may count the scheduler, but that one is shared even to a higher degree in Bulldozer, too.

However, sharing in that context is a good thing, the unified scheduler is more flexible in assigning ALU and AGU Ops to the ALU/AGU pipelines. Nevertheless the theoretical, maximum throughput of Bulldozer is only 2AGU+2ALU ops per clock, whereas a K10 could issue 3+3 in the best case.

Because of the better efficiency, Bulldozer might still have the higher throughput in reality, but the 3 against 4 pipeline picture is still wrong from a technically point of view.

See also here:
http://www.chip-architect.org/news/O...teger_Core.jpg
http://chip-architect.com/news/2003_...it_Core.html#1

(ALUs 0,1,2 and AGUs 0,1,2 are clearly visible, they are not one big shared entity)

I believe the AMD engineers have weighed all the options and have chosen the best configuration.
The ALU and AGUs in Bulldozer are new designs, so it should be much more superior and more efficient than the old designs.

[JkS]

I'm not sure if this has been posted before:

Bulldozer at ISSCC 2011 - The Future of AMD Processors

Some analysis from ISSCC from Pcper, it's worth the read.

This I thought was interesting

Clock gating, which turns off individual components such as execution units, has been much more thoroughly implemented. There is something like 30,000 clock enables throughout the design, and it should allow an unprecedented amount of power savings (and heat reduction) even when the CPU is at high usage rates. Even though a processor might be at 100% utilization, not all functional units are being used or need to be clocked. By having a highly granular control over which units can be gated, overall TDP and heat production can be reduced dramatically even at high utilization rates.

[Aten-Ra]

Clock gating, which turns off individual components such as execution units, has been much more thoroughly implemented. There is something like 30,000 clock enables throughout the design, and it should allow an unprecedented amount of power savings (and heat reduction) even when the CPU is at high usage rates. Even though a processor might be at 100% utilization, not all functional units are being used or need to be clocked. By having a highly granular control over which units can be gated, overall TDP and heat production can be reduced dramatically even at high utilization rates.

If im not mistaken, at HotChips AMD said that Bulldozer will PowerGate the entire Module and not individual components, have I missed something here ??

[rcofell]

If im not mistaken, at HotChips AMD said that Bulldozer will PowerGate the entire Module and not individual components, have I missed something here ??

Power gating != Clock gating;

Power gating involves completely turning off large portions of the design so that no power (well, extremely close to nil) is dissipated. Given the physical complexity and analog characteristics involved (takes time to turn power on/off), this is usually limited to something such as a whole core/module, like you're talking about.

Clock gating is done at a finer granularity and just involves turning off the clock signal to smaller portions of the design that aren't being used, essentially turning off the flip-flops in a piece of logic that doesn't need to change state/be used anyways. Because of this it can be integrated into a design at such an extent.

[Aten-Ra]

I thought it was the same, ok thx

[-Boris-]

I've noticed some stuff. The whole module aproach is to save diespace, the 2 ALUs and shared FPU is all about performance per mm2, and performance per watt. At the same time they made a tradeoff where they sacrificed die space for higher clocks. They have aggressive turbo and energy saving features, maybe the most effective ever.

In other words. They done everything the can to get high performance per watt and mm2, then they've done everything the can in translating this advantage to higher clocks and turbo.

[Opteron146]

I believe the AMD engineers have weighed all the options and have chosen the best configuration.
The ALU and AGUs in Bulldozer are new designs, so it should be much more superior and more efficient than the old designs.

Sure, the 4 BD pipes will certainly be better than the 6old of K8/K10. Nevertheless is is a mistake to just count 3 pipelines for the latter, as it was done in the schematic.

I've noticed some stuff. The whole module aproach is to save diespace, the 2 ALUs and shared FPU is all about performance per mm2, and performance per watt. At the same time they made a tradeoff where they sacrificed die space for higher clocks. They have aggressive turbo and energy saving features, maybe the most effective ever.

In other words. They done everything the can to get high performance per watt and mm2, then they've done everything the can in translating this advantage to higher clocks and turbo.

Congratulations, you understood BD's design philosophy ;-)

[zalbard]

In other words. They done everything the can to get high performance per watt and mm2, then they've done everything the can in translating this advantage to higher clocks and turbo.

That's what AMD is generally about! And it sounds good!

[-Boris-]

Congratulations, you understood BD's design philosophy ;-)

Did for some time, but everytime new information is posted it fits this pattern. Small effective cool cores, made for high clocks, and then turbo and power saving. Which enables clock speeds far above the rated frequency, which until now always has been bound by theoretical and unrealistic 100% usage.
The entire processor seems to be built around their new turbo technology. I wonder if this new turbo technology has something to do with the decision to scrap 45nm BD in favor for an enhanced 32nm BD.

[FlanK3r]

heh, this is nice! Thx to yuri from CZ for the link....
Interlagos !!

[Olivon]

Bulldozer can work on AM3 ?

http://translate.google.fr/translate...oard%2FNews%2F

[spicypixel]

Bulldozer can work on AM3 ?

http://translate.google.fr/translate...oard%2FNews%2F

AFAIK no

[Manicdan]

this is getting annoyingly repetitive

either they found a work around that does not need 900 series chipsets
or were still being lied to.

i think its quite possible to fake compatibility at a loss of some features, but i somehow wonder if that loss is going to be major (like >10% efficiency loss due to simplistic turbo or complete lack of)

[-Boris-]

this is getting annoyingly repetitive

either they found a work around that does not need 900 series chipsets
or were still being lied to.

i think its quite possible to fake compatibility at a loss of some features, but i somehow wonder if that loss is going to be major (like >10% efficiency loss due to simplistic turbo or complete lack of)

We're not being lied to. AMD said that it is possible to make an BD for AM3, but it would be different from those made for AM3+. So they would need two different designs. Which would cost more for AMD than it would be worth. Since enthusiast probably stand for a single digit percentage of overall sales, and many (including me) is upgrading from AM2 and need a new motherboard anyway. While others would go for AM3+ even if they have AM3 because of the performance advantage. The AM3 version would have a very small marketshare if you count OEM, AM2 users and AM3+ upgraders.

If they would go for the fully AM3 compatible design only they would suffer a signigicant performance loss on all models, even if you put them in AM3+ -boards.. And since we not only have much more agressive power saving features, but also a new kind of turbo which uses this new headroom efficiently I think it's a safe bet that we would loose much of the turbo functions, including the boost on all cores. And it seems like the whole turbo business will play a major role in BDs final performance.


Basically AMD has 3 choices.

1: AM3-design only. Suffer a heavy performance loss on all processors, no matter which socket you put them in.
2: Two different designs, much more expensive, and the enthusiasts that upgrade from AM3 would be to few for this to be economically viable.
3 AM3+ only. More performance on all models, cheaper. Probably add some badly needed extra cash from increased motherboard sales too.

[FlanK3r]

no, no and no! Its simple guys,next thinking a lot about it...AM3 socket is not compactible with AM3+ CPUs, because AM3+ CPUs has more pins than AM3 socket! Remember it! But this doesnt mean existing hybrid-AM3+ socket boards with older 800 chipset!

[Olivon]

[Opteron146]

This story is going on and on and on ... and nobody knows anything.

AMD stated last year at a telephone conference that BD wont be AM3 compatible.
Now MSI launched the GD65 a few weeks back, which comes with a mysterious AM3+ printing.
Explanation from MSI: There will be AM3+ (yes, AM3+) CPUs that will fit in the board socket (which has an AM3 socket).
However we know that the AM3b socket has 1 pinhole more. That means, a AM3b CPU that will use that pin, wont mechanically fit into AM3.

The solution now is that AMD will do the same as with Deneb: First launch BD in the old socket AM3, as back then with Phenom2 920&940, and a bit later the real deal with AM3+.

In any case, the (desktop) marketing would have been abysmal bad, lots of people didn't buy AM3 last year, because AM3 was suppose to be a dead end like 1156, thus you buy the product with the better performance, i.e. Intel.

[freeloader]

no, no and no! Its simple guys,next thinking a lot about it...AM3 socket is not compactible with AM3+ CPUs, because AM3+ CPUs has more pins than AM3 socket! Remember it! But this doesnt mean existing hybrid-AM3+ socket boards with older 800 chipset!

Can't we just cut some of the pins off and jam it in the socket?

[FlanK3r]

hehe, then maybe ,-) (secret pin from AMD for beauty appearance )

[RaV666]

We're not being lied to. AMD said that it is possible to make an BD for AM3, but it would be different from those made for AM3+. So they would need two different designs. Which would cost more for AMD than it would be worth. Since enthusiast probably stand for a single digit percentage of overall sales, and many (including me) is upgrading from AM2 and need a new motherboard anyway. While others would go for AM3+ even if they have AM3 because of the performance advantage. The AM3 version would have a very small marketshare if you count OEM, AM2 users and AM3+ upgraders.

If they would go for the fully AM3 compatible design only they would suffer a signigicant performance loss on all models, even if you put them in AM3+ -boards.. And since we not only have much more agressive power saving features, but also a new kind of turbo which uses this new headroom efficiently I think it's a safe bet that we would loose much of the turbo functions, including the boost on all cores. And it seems like the whole turbo business will play a major role in BDs final performance.


Basically AMD has 3 choices.

1: AM3-design only. Suffer a heavy performance loss on all processors, no matter which socket you put them in.
2: Two different designs, much more expensive, and the enthusiasts that upgrade from AM3 would be to few for this to be economically viable.
3 AM3+ only. More performance on all models, cheaper. Probably add some badly needed extra cash from increased motherboard sales too.

You Forgot to mention that all this is your PURE SPECULATION, as we dont have ANY info hardware/software/engineering wise as to why we need AM3+.
Zilch ;-).

[zalbard]

Great find, Olivion. It all makes sense now.
Curious what this pin does, though...

[sutyi]

You Forgot to mention that all this is your PURE SPECULATION, as we dont have ANY info hardware/software/engineering wise as to why we need AM3+.
Zilch ;-).

Bulldozer if I remember correctly uses HT3.1 which basically is a just a simple clock increase from 2.6 to 3.2GHz, meaning 5200MT/s versus 6400MT/s.

AM3 processors work with HT1.0 chipsets... so until the function of that extra pin gets revealed (if there is such) is just the same cattle manure that Intel did by going from LGA1156 > LGA1155.

I know companies need their profit, but in my eye that pins solely purpose just to make people buy a new motherboard with a new chipset if they want the shiny new architecture.

[sutyi]

Great find, Olivion. It all makes sense now.
Curious what this pin does, though...

It makes your wallet emptier...

[Mad Pistol]

It's already been explained that BD is a totally different architecture than Deneb or other Phenom/Athlon based chips. It's made in such a way so that AM3 chips (like Phenom II's) will slot right into AM3+ motherboards, but BD variants (AM3+) will not be able to fit into existing AM3 motherboards.

That's the reasoning that I can tell. Don't change the socket type unless you have to, and in this case, AMD doesn't have to, but BD won't work with existing architectures. Simple.

What part of "Bulldozer is different" do you guys not understand?