What to Expect From AMD at ISSCC 2011

[intangir]

Unlikely, Harvesting Methods like this are not used for high-priced chips.

... what? Where do you think AMD gets its 8-core Magny Cours Opterons??

Processor         Cores  Clock speed  L3 cache  ACP    Price
Opteron 6176 SE   12 	 2.3 GHz      12 MB 	105 W  $1,386
Opteron 6174      12 	 2.2 GHz      12 MB 	80 W   $1,165
Opteron 6172   	  12 	 2.1 GHz      12 MB 	80 W   $989
Opteron 6168   	  12 	 1.9 GHz      12 MB 	80 W   $744
Opteron 6136   	  8 	 2.4 GHz      12 MB 	80 W   $744
Opteron 6134   	  8 	 2.3 GHz      12 MB 	80 W   $523
Opteron 6128   	  8 	 2.0 GHz      12 MB 	80 W   $266
Opteron 6164 HE   12 	 1.7 GHz      12 MB 	65 W   $744
Opteron 6128 HE   8 	 2.0 GHz      12 MB 	65 W   $523
Opteron 6124 HE   8 	 1.8 GHz      12 MB 	65 W   $455

Or Intel its 4 and 6-core Nehalem-EXs?

Processor     Cores/threads Speed     L3 cache  TDP    Price
Xeon X7560    8/16          2.26 GHz  24 MB 	130W   $3,692
Xeon X7550    8/16          2.00 GHz  18 MB 	130W   $2,729
Xeon E7540    6/12          2.00 GHz  18 MB 	105W   $1,980
Xeon E7530    6/12          1.86 GHz  12 MB 	105W   $1,391
Xeon E7520    4/8           1.86 GHz  18 MB 	95W    $856
Xeon L7555    8/16          1.86 GHz  24 MB 	95W    $3,157
Xeon L7545    6/12          1.86 GHz  18 MB 	95W    $2,087
Xeon X7542    6/6           2.66 GHz  18 MB 	130W   $1,980
Xeon X6550    8/16          2.00 GHz  18 MB 	130W   $2,461
Xeon E6540    6/12          2.00 GHz  18 MB 	105W   $1,712
Xeon E6510    4/8           1.73 GHz  12 MB 	105W   $744

Harvesting methods are most definitely used for server chips.

[Mechanical Man]

... what? Where do you think AMD gets its 8-core Magny Cours Opterons??...
Harvesting methods are most definitely used for server chips.

I read it so that harvesting used as so that there is no max chip present at all.

Eg. make 12 core chips, only ever sell 10 core chips.

See the difference with your example?

[intangir]

I read it so that harvesting used as so that there is no max chip present at all.

Eg. make 12 core chips, only ever sell 10 core chips.

See the difference with your example?

Not really. It's done with cache for example. Chips are manufactured with many more cache lines than are actually active. And the Cell processor? It has 8 SPEs, but all the ones you'll find in Playstations only have 7 active.

[Mechanical Man]

Not really. It's done with cache for example. Chips are manufactured with many more cache lines than are actually active. And the Cell processor? It has 8 SPEs, but all the ones you'll find in Playstations only have 7 active.

Whole core is entirely different thing from some catche redundancy or cell (that are not done by AMD or Intel) that has one small core disabled.

[-Boris-]

... what? Where do you think AMD gets its 8-core Magny Cours Opterons??

Processor         Cores  Clock speed  L3 cache  ACP    Price
Opteron 6176 SE   12 	 2.3 GHz      12 MB 	105 W  $1,386
Opteron 6174      12 	 2.2 GHz      12 MB 	80 W   $1,165
Opteron 6172   	  12 	 2.1 GHz      12 MB 	80 W   $989
Opteron 6168   	  12 	 1.9 GHz      12 MB 	80 W   $744
Opteron 6136   	  8 	 2.4 GHz      12 MB 	80 W   $744
Opteron 6134   	  8 	 2.3 GHz      12 MB 	80 W   $523
Opteron 6128   	  8 	 2.0 GHz      12 MB 	80 W   $266
Opteron 6164 HE   12 	 1.7 GHz      12 MB 	65 W   $744
Opteron 6128 HE   8 	 2.0 GHz      12 MB 	65 W   $523
Opteron 6124 HE   8 	 1.8 GHz      12 MB 	65 W   $455

Or Intel its 4 and 6-core Nehalem-EXs?

Processor     Cores/threads Speed     L3 cache  TDP    Price
Xeon X7560    8/16          2.26 GHz  24 MB 	130W   $3,692
Xeon X7550    8/16          2.00 GHz  18 MB 	130W   $2,729
Xeon E7540    6/12          2.00 GHz  18 MB 	105W   $1,980
Xeon E7530    6/12          1.86 GHz  12 MB 	105W   $1,391
Xeon E7520    4/8           1.86 GHz  18 MB 	95W    $856
Xeon L7555    8/16          1.86 GHz  24 MB 	95W    $3,157
Xeon L7545    6/12          1.86 GHz  18 MB 	95W    $2,087
Xeon X7542    6/6           2.66 GHz  18 MB 	130W   $1,980
Xeon X6550    8/16          2.00 GHz  18 MB 	130W   $2,461
Xeon E6540    6/12          2.00 GHz  18 MB 	105W   $1,712
Xeon E6510    4/8           1.73 GHz  12 MB 	105W   $744

Harvesting methods are most definitely used for server chips.

Intel or AMD has never done what he was talking about. There is no reason to start now. A 12 core BD would be much larger than 10 or 8 core BDs.

[intangir]

Intel or AMD has never done what he was talking about. There is no reason to start now. A 12 core BD would be much larger than 10 or 8 core BDs.

There are all sorts of things Intel and AMD haven't done that they could start doing if they so desire.

And how exactly do you make a rectangular region that fits 5 modules but not 6? Why do you think there have been no 3-module dies proposed?

Have you seen Bob Colwell's lecture for Stanford's EE380 colloquium, where he talks about how shrinking the Pentium's FPU had no impact on die size? "If you take out Kansas, North Dakota and Texas are still the same distance apart!"

[-Boris-]

There are all sorts of things Intel and AMD haven't done that they could start doing if they so desire.

And how exactly do you make a rectangular region that fits 5 modules but not 6? Why do you think there have been no 3-module dies proposed?

Like this:



Less than 9% larger than an 8 core.
A 12 core is 40% larger if you add 2 modules on a 8 core.

A 10 core is good business since it wastes less space. A 12 core don't, it's a lot harder to produce.

[intangir]

A 10 core is good business since it wastes less space. A 12 core don't, it's a lot harder to produce.

Not if you get higher yields on the 12-core, since only 5 out of 6 modules = 83% need to work.

How would they route the cache traffic between the five L3 blocks? I doubt that 5-module photoshop is a feasible design. It at least would need more space for the crossbar than the 4-module design. Your numbers don't look likely to me.

[-Boris-]

Not if you get higher yields on the 12-core, since only 5 out of 6 modules = 83% need to work.

How would they route the cache traffic between the five L3 blocks? I doubt that 5-module photoshop is a feasible design. It at least would need more space for the crossbar than the 4-module design. Your numbers don't look likely to me.

They might not even have 5 cache blocks, they may be settling for 4 anyway. Try to fit 6 modules and cache blocks in less than 40% larger die space.

And we have official roadmaps mentioning 10 core BDs. We don't have any roadmap mentioning 12 cores. So lets see how it turns out.

[rcofell]

Like this:



Less than 9% larger than an 8 core.
A 12 core is 40% larger if you add 2 modules on a 8 core.

A 10 core is good business since it wastes less space. A 12 core don't, it's a lot harder to produce.

Nice design if photoshop is your CAD tool
However I suspect there are at least a handful of reasons why it's not such a simple matter

1. Just because those areas "look" like empty space doesn't necessarily mean they are, there's a strong chance a bit of it is synthesized logic, which hides itself well in the black & white photos. Compare the top part of the colored core to the rest of the chip to see an example (unless there's additional intentional obfuscation).

2. The photo doesn't show the interconnect/wiring track congestion at the higher levels, which could negate the ability to use such space.

3. [More nitpicky] L3 cache accesses appear to go through the crossbar (as opposed to Intel's ring bus), so who's to say how much additional wiring complexity/area would result from adding another core following the same methodology? The impact on latency would certainly be a factor too.

[intangir]

They might not even have 5 cache blocks, they may be settling for 4 anyway. Try to fit 6 modules and cache blocks in less than 40% larger die space.

I strongly suspect that the module-L3 interconnect is a set piece of design that is done once and then replicated for each module. If they dissociate the number of L3 blocks from the number of modules, they would have to special-case route each module's interconnect, which would blow up the engineering effort required.

And there are latency issues involved too, as rcofell mentioned. They might have to redesign the module to tolerate variable distances to the closest L3 block, or worse, use two types of modules.

And we have official roadmaps mentioning 10 core BDs. We don't have any roadmap mentioning 12 cores. So lets see how it turns out.

Yes, let us see.

[-Boris-]

Nice design if photoshop is your CAD tool
However I suspect there are at least a handful of reasons why it's not such a simple matter

1. Just because those areas "look" like empty space doesn't necessarily mean they are, there's a strong chance a bit of it is synthesized logic, which hides itself well in the black & white photos. Compare the top part of the colored core to the rest of the chip to see an example (unless there's additional intentional obfuscation).

2. The photo doesn't show the interconnect/wiring track congestion at the higher levels, which could negate the ability to use such space.

3. [More nitpicky] L3 cache accesses appear to go through the crossbar (as opposed to Intel's ring bus), so who's to say how much additional wiring complexity/area would result from adding another core following the same methodology? The impact on latency would certainly be a factor too.

I did it in paint.

But yes, I understand all that. But adding 2 modules won't make the problem easier. My picture is only a suggestion, and since AMD talks about 10 cores and not 12 cores. I can't be to far off. Let me be the first to say that I would be a bit suprised if the 10 core would look like my picture. But I think some resemblance is possible.

[rcofell]

I did it in paint.

But yes, I understand all that. But adding 2 modules won't make the problem easier. My picture is only a suggestion, and since AMD talks about 10 cores and not 12 cores. I can't be to far off. Let me be the first to say that I would be a bit suprised if the 10 core would look like my picture. But I think some resemblance is possible.

Yeah, I'm not disputing the fact a 5/6 module is possible/in the pipeline or your "artistic representation"

I was just trying to point out the fallacy in considering the "empty spaces" to really be empty and available for more components