What to Expect From AMD at ISSCC 2011

[Opteron146]

You Forgot to mention that all this is your PURE SPECULATION, as we dont have ANY info hardware/software/engineering wise as to why we need AM3+.

We had some marketing info:

"When we initially set out on the path to Bulldozer we were hoping for AM3 compatibility, but further along the process we realized that we had a choice to make based on some of the features that we wanted to bring with Bulldozer. We could either provide AM3 support and lose some of the capabilities of the new Bulldozer architecture or, we could choose the AM3+ socket which would allow the Bulldozer-base Zambezi to have greater performance and capability.

The majority of the computer buying public will not upgrade their processors, but enthusiasts do. When we did the analysis it was clear that the customers who were most likely to upgrade an AM3 motherboard to a Bulldozer would want the features and capability that would only be delivered in the new AM3+ sockets. A classic Catch-22.

Why not do both you ask? Just make a second model that only works in AM3? First, because that would greatly increase the cost and infrastructure of bringing the product to market, which would drive up the cost of the product (for both AMD and its partners). Secondly, adding an additional product would double the time involved in many of the development steps.

So in the end, delivering an AM3 capability would bring you a less featured product that was more expensive and later to market. Instead we chose the path of the AM3+ socket, which is a path that we hope will bring you a better priced product, with greater performance and more features - on time.

When we looked at the market for AM3 upgrades, it was clear that the folks most interested in an AM3-based product were the enthusiasts. This is one set of customers that we know are not willing to settle for second best when it comes to performance, so we definitely needed to ensure that our new architecture would meet their demanding needs, for both high performance and overclockability. We believe they will see that in AM3+."

http://www.planet3dnow.de/cgi-bin/ne...?id=1282840508

I really wonder why AMD should have changed that decision now. Maybe the MSI people were smoking something weired ...

[-Boris-]

You Forgot to mention that all this is your PURE SPECULATION, as we dont have ANY info hardware/software/engineering wise as to why we need AM3+.
Zilch ;-).

We have AMD saying that they could do it, but the performance disadvantage wouldn't be to big since some features wouldn't work. That's the truth, yhe speculative part is my thought about these features being power saving features enabling the new turbo technology.

Bulldozer if I remember correctly uses HT3.1 which basically is a just a simple clock increase from 2.6 to 3.2GHz, meaning 5200MT/s versus 6400MT/s.

AM3 processors work with HT1.0 chipsets... so until the function of that extra pin gets revealed (if there is such) is just the same cattle manure that Intel did by going from LGA1156 > LGA1155.

I know companies need their profit, but in my eye that pins solely purpose just to make people buy a new motherboard with a new chipset if they want the shiny new architecture.

It probably has nothing to do with hyper transport. There is nothing that points in that direction. My guess is that it's limiting performance since the power saving features and thus the new turbo won't work as good. If so AM3 would lower the performance in pretty much all workloads.

[DarthShader]

You Forgot to mention that all this is your PURE SPECULATION, as we dont have ANY info hardware/software/engineering wise as to why we need AM3+.
Zilch ;-).

We do - it's connected with the new Turbo and power savings modes, something about more advanced voltage control or so - can't remember exactly anymore.

[RaV666]

We have AMD saying that they could do it, but the performance disadvantage wouldn't be to big since some features wouldn't work. That's the truth, yhe speculative part is my thought about these features being power saving features enabling the new turbo technology.



It probably has nothing to do with hyper transport. There is nothing that points in that direction. My guess is that it's limiting performance since the power saving features and thus the new turbo won't work as good. If so AM3 would lower the performance in pretty much all workloads.

We do - it's connected with the new Turbo and power savings modes, something about more advanced voltage control or so - can't remember exactly anymore.

Thing is, for one, disabling turbo alltogether doesnt mean the cpu should not work entirely.
I was referring to hardware/engineering obstacles that would prevent BD chips from working on the AM3 socket.
Yes ,there was a blurb about their "choices", but no concrete information as to why this wasnt possible.
And Boris your whole post was speculative ,we dont know what the performance hit could be,or why ,or if any.Because there is no HARD FACT info about it.You just made many assumptions based on a marketing blurb.Which may be or may not be true.
Going from AM2 to AM2+ ,in pure reality ,performance loss was neglible, yes, there was some feature loss.But in the end it worked almost as good when manually setting platform.

@Mad pistol
Think about it for a second, if it WAS such a strong departure from existing infrastrcture as you say it is, it would not work with basically the same socket (sans different keying), that works with current chips using the same chipsets and type of bus .And morover, it would not be a DROP IN replacement in server arena.
Boris seems to be closer to the truth, some voltage/turbo related feature that needs more advanced power distribution seems more likely, however it would imply the cpu itself should work just fine without it on regular AM3.

[undone]

UPDATE 3:

Hiroshige Goto has a nice photo about bulldozer, maybe more accurate than ever.(Article is in Japanese)

http://pc.watch.impress.co.jp/docs/c...01_430044.html

[JF-AMD]

None of the info on AM3 w/BD is from AMD.

If this turns out to not be true, which I suspect is the case, don't get mad. I doubt we would have said it doesn't work if it actually did. I am guessing that because this is from a third party document that is translated from the original.

[madcho]

There is die space empty on the BD core or it's me ?

omg !

[JF-AMD]

That is where we are hiding the flux capacitor. Don't tell anyone.

[Opteron146]

None of the info on AM3 w/BD is from AMD.

If this turns out to not be true, which I suspect is the case, don't get mad. I doubt we would have said it doesn't work if it actually did. I am guessing that because this is from a third party document that is translated from the original.

Actually, I would get mad, if it would work, because you stated earlier last year that it does not.

That is where we are hiding the flux capacitor. Don't tell anyone.

Ahh come on ... dont hide something useless like a flux capacitor, better hide something useful like a dedicated directory cache ;-)

[JkS]

JF, I was wondering, since the Bulldozer architecture is modular, and previous slides have shown the next gen bulldozer to be upto 10cores.

Why do a 10 core, when it would make more sense to do a 12 core (in my eyes) so then a rectangle die can be cut out instead of an odd shape?

10 core I assume would be:
[x][x][x]
[x][x]

and a 12 core would be
[x][x][x]
[x][x][x]

[informal]

There is a power limit on a socket level and a power limit that your microacrhitecture and process allows for certain class of parts. They will manage to increase core count next year by 25% with 20C improved Bulldozer cores compared to 16C interlagos we will have soon on the market. The improved cores will probably mean faster with better power characteristics. You will have also 25% more headroom to run your Turbo up,which will be good for poorly threaded server workloads. Similar applies to Komodo on desktop,if it ships with 10 cores next year. It's 25% more cores,which should be "enhanced", within 125W TDP envelope and with a bit higher TDP headroom for Turbo. All this on the same process node .

[Oliverda]

There is die space empty on the BD core or it's me ?

omg !

It's not a big deal at all. SB has a dead space as well.

[Opteron146]

JF, I was wondering, since the Bulldozer architecture is modular, and previous slides have shown the next gen bulldozer to be upto 10cores.

Why do a 10 core, when it would make more sense to do a 12 core (in my eyes) so then a rectangle die can be cut out instead of an odd shape?

10 core I assume would be:
[x][x][x]
[x][x]

and a 12 core would be
[x][x][x]
[x][x][x]

Easy answer, because it will be sth like:
[x][x][x]
[x][x][y]

Where y = unknown.
Partly it will be used up by PCIe, maybe they add a directory cache, too, maybe something else ... but you can bet that they wont do anything unnecessarily ;-)

[Aten-Ra]

Hmmm, dual module BD with 4MB L3 ??

[JkS]

Hmmm, dual module BD with 4MB L3 ??

What about it? Makes perfect sense

[informal]

What about it? Makes perfect sense

4 cores,4MB of L2 + 4MB of L3,crazy high Turbo,very high default clock,very good power draw figures,smaller die area than QC Deneb maybe even smaller than Propus.What's not to like ?

[-Boris-]

JF, I was wondering, since the Bulldozer architecture is modular, and previous slides have shown the next gen bulldozer to be upto 10cores.

Why do a 10 core, when it would make more sense to do a 12 core (in my eyes) so then a rectangle die can be cut out instead of an odd shape?

10 core I assume would be:
[x][x][x]
[x][x]

and a 12 core would be
[x][x][x]
[x][x][x]

They already have som empty space between two of the modules, if you squeez anither module in between them and add some empty space between the other modules next to the NB it will be around the same amount of dead space.

xx=module
e= Empty space
n= North Bridge

8X:
[xx][e][xx]
[xx][n][xx]

10X:
[xx][xx][xx]
[xx][en][xx]

12X:
[xx][e][xx][xx]
[xx][n][xx][xx]


Or the small empty area could be used for extra cache:



EDIT:
There, fixed it.
Click to open larger pic. 10 core with 10Mb L3 and 10Mb L2 is just 8,8% larger, and I haven't even squeezed it.

EDIT2:
Added an extra row of modules in the same way to make a 12core. It was 40% larger than the 8 core. Hardly worth the 50% increase in cores. Then 9% larger die to get 20% more cores looks much more promissing.

[Aten-Ra]

I mean that it will be made with only 2x 2MB L3, it will not have 8MB and 4MB disabled, that's why the empty space between the two modules.

[kuroikenshi]

That is where we are hiding the flux capacitor. Don't tell anyone.

No thanks John, I prefer Family Guy's spin off in "Black to the Future"
http://www.youtube.com/watch?v=LIAYLxaAed0

[EvilOne]

Easy answer, because it will be sth like:
[x][x][x]
[x][x][y]

Where y = unknown.
Partly it will be used up by PCIe, maybe they add a directory cache, too, maybe something else ... but you can bet that they wont do anything unnecessarily ;-)

They will prob add an extra module inside [y] to help getting a higher % of working chips during manufacturing. Easier to get 5 out of 6 working then 5 out of 5.

Maybe some nice unlocks in the future if they do it that way too

[cesariuth]

what about of integrate the NB in the next gen?

[JkS]

what about of integrate the NB in the next gen?

That would happen if they integrate the PCIe as Opteron146 mentioned, but it would also mean we need a new socket/platform (which would be very welcome for small form factors!)

[Opteron146]

They will prob add an extra module inside [y] to help getting a higher % of working chips during manufacturing. Easier to get 5 out of 6 working then 5 out of 5.

Unlikely, Harvesting Methods like this are not used for high-priced chips.
They would try to sell the full chip in any case. The defect ones could still be sold in the desktop segment.
Maybe AMD is planning this, Komodo is labeled as 8core CPU in the roadmap pictures, i.e. one module is probably deactivated there.

The integration of PCIe will use up some die space, just have a look of the PCIe area of Intels 1155/56 chips. Now imagine that AMD will pack 32 Lanes in the chip, not only 16 as in Linnfield / Sandy, and we have quite a big area.

[-Boris-]

They will prob add an extra module inside [y] to help getting a higher % of working chips during manufacturing. Easier to get 5 out of 6 working then 5 out of 5.

Maybe some nice unlocks in the future if they do it that way too

No, that wouldn't happen. If so they still would have som rare 12 cores sold for high prices.

10 cores is most likely since it's the most effective design compared to consumed die area.

[Manicdan]

4 cores,4MB of L2 + 4MB of L3,crazy high Turbo,very high default clock,very good power draw figures,smaller die area than QC Deneb maybe even smaller than Propus.What's not to like ?

the only thing not to like is that a 65w quad BD might turbo very little compared to an 8 core 125w beast.

if your game uses 4 threads, you have 16.25w per thread in the 65w envelope. and the 125w envelop would have 31.25w per thread, assuming some need a few watts to idle, lets just say its ~28w per thread, still 75% more headroom.

while this means nothing for us overclockers, this could mean that reviews show 8 core chips just raping the 4 core versions across the board.

which then makes the quads worth less and thus cheaper and easier for us to get our hands on them