Intel plans to deliberately limit Sandy Bridge overclocking

[informal]

SB has AVX, which may do 1 256-bit SSE instruction or may fuse 2 128-bit SSE instructions into 1 256-bit instruction.

We all know SB has AVX,it's been known for a while... We do not know how they managed the increased throughput with no die area investment(hence the double pumped proposition).

edit: Also,the thread title is a bit misleading,intel didn't do this deliberately ,it's just the part of the design.It's not like they made it this way just for the sake of preventing people from OCing these chips.