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Thread: Intel plans to deliberately limit Sandy Bridge overclocking

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  1. 07-23-2010, 10:21 AM #10
    Hans de Vries
    Hans de Vries is offline
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    Quote Originally Posted by informal View Post
    Sweeper,the 6MBs are actually the usable part of the 8MBs,like Hans explained in the link i posted above... Read up.That's why Hornet asked about the 1.5Mbs of cache dedicated to each core.
    Yes, This is why you can have a Sandy Bridge with disabled GPU and 8MB L3 cache (2MB per core).

    http://www.xtremesystems.org/forums/...10&postcount=1


    Regards, Hans
    Last edited by Hans de Vries; 07-23-2010 at 10:23 AM.
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