Intel plans to deliberately limit Sandy Bridge overclocking

[Hans de Vries]

This is incorrect assemptions. Can't say more, but this is pure speculation in the wrong direction, Sorry for the bad news. (The size of the cache and the GPU cache needs are not related, good imagination by the way ;-) )
(The other questions answers are under NDA ... sorry)
The good new is that the title of this thread is totally silly and wrong too

This thread was just a Big piece of
Francois

Hi, François,

I have no problem in believing you that the title of this thread,
(which is the title of the article it refers to) is crap and fud.

For the other part, the architectural features of Sandy Bridge,
there is an ancient saying in Dutch which goes as follows:

"An old grinning Monkey does not need to have signed an NDA
to see some things from a mile away...."

So for those who ask me I'll say:

1) The L3 cache located next to each core is 2MB.
2) The AVX unit of Sandy Bridge is two fold hiper-pipelined.

(It handles 256 bit SIMD words with 128 bit hardware by
inserting the second 128 bit data into the pipeline after
half a cycle after the intermediate results of the first half
are stored in the halfway registers)


Regards,


But I respect that your position on this is like: