oh stop it, always teasing with all the things you know and then not telling anything :P
at least hint at whats wrong so i can try to find an answer somewhere else :P
oh come on guys! dont tell me i got it all wrong and its misleading and then leave me standing in the rain :P
at least hint at what was misleading... calling cache associativity cache width?
i wrote it, and thats not true about it?
where have they said that? and how would they achieve significant ipc improvements?
they havent mentioned anything that could potentially improve ipc significantly...
they ALWAYS say that for EVERY new cpu... they said that about nehalem as well and it ended up with almost the same ipc in most apps as c2d... :P
revamped cache, i mentioned that...
so reducing the L3 cache from 4 to 3mb and reducing it from 16way to 12way associative and THEN sharing it not only between 2 cores but the gpu as well... thats improving ipc how? :P
and that affects ipc how...? :P
new instructions will result in a boost in a few apps only at launch, if even that... i wouldnt count this as ipc boost, and you said you "heard" ipc improvements beyond avx, right?
this adjusts clocks, not ipc... so again, where are those ipc improvements intel supposedly raved about? :P
yeah, thats a good point... now its 100mhz steps and not 133 anymore... wont make a huge difference but should help a bit to maybe get higher turbo multis and lower idle clocks![]()









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