[NEW STUFF] Intel LGA1155

[saaya]

Some of their conclusions are pretty misleading (A2 stepping, VRM13, 115X, etc...), however some are pretty true

really? whats misleading?

btw, thats me... i wrote that thing yesterday night... at 3am... so please dont burn me for getting something wrong ^^

Actually pineview has no FSB and both (mem controller and graphics) are integrated in on the same silicon die.

really? according to anandtech intel told him it does... and it perfectly explains the memory latency?

But this dosn't matter because they still comunicate through a main memory. Cache coherent buses (like HTT or QPI) only make sence when cores have a similar cache subsytem. BTW, this applies also to AMD fusion which means that althrough GPU and CPU cores are integrated on the same die, the data exchange will go through the main memory.

i thought they are hooked up to an internal switch? like the xbar between cores and imc on amds multi core cpus?

If I recall correctly, upcoming SB is the only cpu which has different type of cores connected to the same L3 cache. I wonder if Intel will furter improve their GPU drivers to get some help from a SB cores in heavy vertex/geometry calcultions (especialy that SB has doubled its floating point performance relatively to nehalem).

would make sense... but that would be tricky to load balance with turbo on both cpus and igp... and did it really help a lot on the current implementation? it helps a lot in benchmarks where the cpu is idle, but in games it only gave a 5% boost or so iirc?

I just look and giggle

hey :P
at least tell me what i got wrong then :P
its not like i want to spread nonsense... please lmk!