I think all the performance speculations are useless at this stage. I'll bet you have no appropriate background to estimate a performance bust from an additional L1 load port, much bigger loop detector buffer, lower cache latencies, larger L3 bandwidth (and other Sandy Bridge features which yet to be disclosed). What Intel does disclosed is a performance speedup (1.42x - 2.57x) for AVX vs. SSE for various FP workloads. Also confirmed on actual Sandy Bridge silicon.
http://software.intel.com/en-us/arti...lation-slerp//




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