Quote Originally Posted by saaya View Post
just look at pineview it still has the fsb interface for block to block communication within the same die... LOL

i wonder if sandybridge still uses qpi for block to block communication...
Actually pineview has no FSB and both (mem controller and graphics) are integrated in on the same silicon die. But this dosn't matter because they still comunicate through a main memory. Cache coherent buses (like HTT or QPI) only make sence when cores have a similar cache subsytem. BTW, this applies also to AMD fusion which means that althrough GPU and CPU cores are integrated on the same die, the data exchange will go through the main memory. If I recall correctly, upcoming SB is the only cpu which has different type of cores connected to the same L3 cache. I wonder if Intel will furter improve their GPU drivers to get some help from a SB cores in heavy vertex/geometry calcultions (especialy that SB has doubled its floating point performance relatively to nehalem).