Quote Originally Posted by A-Grey View Post
All he needs is the register offsets that hold the DRAM Clock Fine Delays to know what register to save in BAR_Edit so he can load them automatically at next boot to always have the same value.

This probably works very well when you don't have a dual boot configuration with Linux like I have.
Problem is you can't just change those values on their own.

Channel 1 DLL fine delays
FED14500 00000000 00000000 00004577 0000B033
FED14510 0000BB4A 00000062 00000940 00000018
FED14520 00002016 0000020A 00001B01 00000000
FED14530 00003332 00000924 00000924 00000800

Channel 2 DLL fine delays
FED14900 00000000 00000000 00002566 00009B11
FED14910 0000CC4A 00000C3E 000005EB 0000001A
FED14920 000004B4 0000020B 00001B01 00001121
FED14930 00003432 00000924 00000924 00000C00

The bold/underline are fine control delay/fine clock delay.
The underline are registers of interest for possibly phase degree offset.