Quote Originally Posted by mikeyakame View Post
I know the register offsets which hold these values, and I can explain the few that I've worked out, but I still cant for the life of me figure out the method for obtaining the actual fine delay in PS for each DLL table entry. I've worked out where I think fine delay ps bitmask is, and where some of the manually input phase degree offsets are set. I still can't get consistent results reversing the register values though.

I've run out of ideas on how to get the correct reverse data from the bitmasks/hex value. I believe I am missing the key element to how they are input by Intel, all I've got is educated assumptions to work with.
All he needs is the register offsets that hold the DRAM Clock Fine Delays to know what register to save in BAR_Edit so he can load them automatically at next boot to always have the same value.

This probably works very well when you don't have a dual boot configuration with Linux like I have.