X48 Rampage Formula Preview.

[Alien Grey]

@mikeyakame

Do you know if you leave the CPU and NB Clock Skew on Auto that they automatically change when you use higher or lower FSB?

[kuebk]

I use CPU Clock Skew Delay 200ps and NB Clock Skew Delay 100ps. This lets me run stable with 1.33V for North Bridge Voltage in the BIOS. Without these delays it isn't possible for me to get it stable with that low voltage. Maybe with my Quad it would be impossible to have that stable without the delays.

DRAM CLK on Channel A/B is on Auto.

Yea, but I'm using C2D not C2Q.

[Alien Grey]

Yea, but I'm using C2D not C2Q.

It doesn't matter try it anyway.

Try with CPU Clock Skew Delay 100ps and NB Clock Skew Normal. Or both Delayed 100ps.

I didn't need more than 200ps for CPU Clock Skew and 100ps for NB Clock Skew.

[kuebk]

It doesn't matter try it anyway.

Try with CPU Clock Skew Delay 100ps and NB Clock Skew Normal. Or both Delayed 100ps.

I didn't need more than 200ps for CPU Clock Skew and 100ps for NB Clock Skew.

That may sound dumb, but will changing CPU skew raise my MEM stability?

TBH I was rather thinking to start messing out with NB GTL or DRAM REF voltages and maybe with trying to raise tREF, too bad there is no option in bios to set it up directly from it.

[Alien Grey]

That may sound dumb, but will changing CPU skew raise my MEM stability?

TBH I was rather thinking to start messing out with NB GTL or DRAM REF voltages and maybe with trying to raise tREF, too bad there is no option in bios to set it up directly from it.

That depends on where the problem is situated. When it's your memory that makes errors it won't make any difference. You can only see that when you try it.

[kuebk]

That depends on where the problem is situated. When it's your memory that makes errors it won't make any difference. You can only see that when you try it.

Yea, but could you give me any advice from which should I start? :p

[Alien Grey]

Yea, but could you give me any advice from which should I start? :p

Start with the CPU Clock Skew Delay 100ps and NB Clock Skew Normal. If that doesn't work try CPU Clock Skew Delayed 100ps and NB Clock Skew Delayed 100ps. Still no luck CPU Clock Skew Delayed 200ps and NB Clock Skew Delayed 100ps.

Lower your NB voltage and run Prime95. It doesn't matter if it fails within 15 minutes. It's just to find what settings work good for you.

[kuebk]

Can CPU/NB skews enchance DRAM overclock ability?

[Alien Grey]

Can CPU/NB skews enchance DRAM overclock ability?

Nope, my OCZ Reaper HPC PC2-8500 didn't clock any further with adjusting CPU and NB Clock Skew. At DDR 1117MHz and tRD 7 they are at there maximum with my Q9450@3.72GHz.

[kuebk]

Nope, my OCZ Reaper HPC PC2-8500 didn't clock any further with adjusting CPU and NB Clock Skew. At DDR 1117MHz and tRD 7 they are at there maximum with my Q9450@3.72GHz.

That's why I was kinda confused about your advices when I asked how could I enchance DRAM overclocking ability not how to enchance CPU overclocking ability.

So with what should I mess to get more stable DRAM?

[Mikefra2008]

In order that estan the options in the bios? dram skel chanel a y b=? If I want that you advise me with it I do not like to have things auto

[Alien Grey]

In order that estan the options in the bios? dram skel chanel a y b=? If I want that you advise me with it I do not like to have things auto

My OCZ Memory likes Normal or Delay 50ps. They were running at their maximum speed on Auto and changing the DRAM CLK Skew on Channel A/B didn't make them run stable above 1117MHz.

With the DRAM Clock Fine Delays at 4T I've got the best stability with these sticks at 1117MHz. You can see what your Clock Fine Delays are in EVEREST.

For higher speed you might need longer timings. The Clock Fine Delays for my G.SKILL Memory at 1199MHz are longer. I can't verify it at the moment what timings they are.

----------

I checked my DRAM Clock Fine Delays at DDR 1199 and they are 11T for Channel A1 and B1 and 9T for Channel A2 and B2.

[Mikefra2008]

Does Do you use fsb strap400? Try mean fsb strap 266 and 200 and one cannot though it uses fewer mhz in the memory


If your you use fsb strap better(best) dividing minor You were managing

[Alien Grey]

Does Do you use fsb strap400? Try mean fsb strap 266 and 200 and one cannot though it uses fewer mhz in the memory


If your you use fsb strap better(best) dividing minor You were managing

Yes, FSB Strap 400MHz and tRD 6 is the best you can do.
If you use strap 333MHz you're going to have to use tRD 7 and strap 266MHz is to tight for FSB > 425MHz.

[RedBull1985]

I have tried almost EVERYTHING to get my system stable @ 500Mhz and Ram 1:1.....the most frustrating part is that it boots to WIndows 99% of the time, can browse, listen to music,watch CD-rips....but once i go HD rips,compressing archives or stress testing , it fails RANDOMLY and guess what? NO BSODs now.....just hangs there.

I am not even OCing the ram, its \rated to be run @ 500Mhz and yet , it just hangs in WIndows even after passing Memtest86+...so so frustrating experience with the 500 FSB.and oh yea, the board is rock solid @ 495 btw.....

[Mikefra2008]

ram 1:1 very bad ram 3:5 very nice

[mikeyakame]

Haven't tried to use CPU/NB Skews, same as I haven't with NB GTL and tREF.

About CPU - it's not its fault for 100%.
I've used to run my rig on [IP35-PRO]:
FSB = 450
MEM = 540
vCPU = 1.375
vDDR = 2.2
Timings = 5-5-5-15

And on Rampage Formula I added
LLC = Enabled
A/B Skews = Advance +300

All other settings on stock/default/auto settings and haven't got any stability problem back before when I was using IP35-PRO and now when I'm using Rampage Formula.

IMO the problem is with my RAM, I'm not sure can it be clocked so high.

Anyway I'm kinda curious why my mobo can run ram at 540 on stock vMCH but to get 600 I need to raise it by 0.2v.

Gah XS timed out and lost my huge post. I'm not going to write it all again.

Basically as you increase DDR frequency MCH load increases, and voltage jitter limits decrease at the same time, so increasing Vddr to 2.4v lets say to get 1200mhz while using 1.55v Vmch to run 475mhz fsb at PL6 and 1.40v Vcc to run 4.2ghz, you might push the Vreg electronics to the point where 95% of the circuit operates correctly at say 90c, but 5% of the electronics can't guarantee the same consistent operational behaviour as the other 95%, this appears as instability, inconsistenly and errors.

Lets say 100% of the circuit meets operational specs at 85c with 90% output of its maximum, but your circuit is operating below 85c at 95% capacity at 75% output load, but once the output load increases past 75%, Vreg circuitry temps begin to shoot upto 95c in some areas and it just happens these areas also contain say 5% of electronic components which fail to meet operational specs at 95c and > 75% output, but the other 95% don't show any signs of faltering. You might pick up 1-2% of loss from the rest of the components over compensating, but you still have 3% which can not be compensated by the rest of the components working at their limits.

Nothing is perfect, and you need to sacrifice voltages sometimes to guarantee stability for the rest, Vddr then Vmch are usually the first ones that need slight reductions, if this means you lose some headroom and performance you have no choice, as the gains from PL/DDR frequency are much smaller than FSB/CPU frequency, and more important Vtt/Vcc filtering circuitry are designed to be much more robust and more importantly be broad enough to cope with scenarios that may occur only in 0.0001% of operation, but are bad enough to throw a stable system into a BSOD or corruption. It's more likely that CPU voltage is going to be increased rather than DDR, and GTL+ bus design is more sensitive to this kind of random occurance than DDR bus is.

[kuebk]

I checked my DRAM Clock Fine Delays at DDR 1199 and they are 11T for Channel A1 and B1 and 9T for Channel A2 and B2.

You have your sticks in A1/B1 or A2/B2?

And did you change it manually or it was in MEM SPD? What tREF do you have? Or maybe could you screenshot Everest Chipset info?

Gah XS timed out and lost my huge post. I'm not going to write it all again.

Basically as you increase DDR frequency MCH load increases, and voltage jitter limits decrease at the same time, so increasing Vddr to 2.4v lets say to get 1200mhz while using 1.55v Vmch to run 475mhz fsb at PL6 and 1.40v Vcc to run 4.2ghz, you might push the Vreg electronics to the point where 95% of the circuit operates correctly at say 90c, but 5% of the electronics can't guarantee the same consistent operational behaviour as the other 95%, this appears as instability, inconsistenly and errors.

Lets say 100% of the circuit meets operational specs at 85c with 90% output of its maximum, but your circuit is operating below 85c at 95% capacity at 75% output load, but once the output load increases past 75%, Vreg circuitry temps begin to shoot upto 95c in some areas and it just happens these areas also contain say 5% of electronic components which fail to meet operational specs at 95c and > 75% output, but the other 95% don't show any signs of faltering. You might pick up 1-2% of loss from the rest of the components over compensating, but you still have 3% which can not be compensated by the rest of the components working at their limits.

Nothing is perfect, and you need to sacrifice voltages sometimes to guarantee stability for the rest, Vddr then Vmch are usually the first ones that need slight reductions, if this means you lose some headroom and performance you have no choice, as the gains from PL/DDR frequency are much smaller than FSB/CPU frequency, and more important Vtt/Vcc filtering circuitry are designed to be much more robust and more importantly be broad enough to cope with scenarios that may occur only in 0.0001% of operation, but are bad enough to throw a stable system into a BSOD or corruption. It's more likely that CPU voltage is going to be increased rather than DDR, and GTL+ bus design is more sensitive to this kind of random occurance than DDR bus is.

The problem is that my current CPU is walled around ~465fsb.

[mikeyakame]

You have your sticks in A1/B1 or A2/B2?

And did you change it manually or it was in MEM SPD?

Clock fine delay is set according to DRAM DLL selection, flight time calculation, and aggressiveness of cross clocking phase timing. The 11T value is a delay gate insert timing for the MCH, it doesn't really mean much in terms of an accurate PS delay skew. Changing DRAM fine clock delays (clock skews) works through additional DLL delay gate offset, achieved through two values.

1) Selecting the bitmask for fine delay adjustment from at intervals of 5ps, at 16 points, from 5-80ps. This is global for all DLL tables, and all dimm slots.
2) Selecting bitmask for phase degree offset of DLL fine delay value you want to manually set, this a 5 bit mask of 0-31, which gives 31 degrees of offset.

DRAM clock skew adjustment is done through the above method, the 11T itself means nothing as there is additional offset applied through bitmask of phase degrees and fine delay ps at the MCH. 11T could mean 770ps or it could mean 440ps, it is only relevant to delay gate insert timing for the current flight time calculations at POST, and not actual dram fine delay skew ps values, as it can change from boot to boot and still actually be a value within 20ps of another boot.

You have your sticks in A1/B1 or A2/B2?

And did you change it manually or it was in MEM SPD? What tREF do you have? Or maybe could you screenshot Everest Chipset info?



The problem is that my current CPU is walled around ~465fsb.

It was just an example, don't need to take it so literally. If your CPU walls at 465FSB, then you find that around 457-461fsb will be the sweet spot if gtl's and such are set up right. The point I was trying to make though was that as you get closer to the "WALL" of either the CPU, MCH or DRAM frequencies you require smaller operational limits to guarantee stable operation. This becomes harder to achieve the closer your get, and minute inconsistencies can break what appears to be perfect stability. You have much smaller room for error, which to guarantee small band of error requires much more stable voltage input from PSU, and your board's Vreg also has to give much more stable operation, which on any many boards of the same model gives wildly varying results with same components. You might find 1 in 100 will do it, but the other 99 will either fail completely or fail occasionally.

[Alien Grey]

That's why I was kinda confused about your advices when I asked how could I enchance DRAM overclocking ability not how to enchance CPU overclocking ability.

So with what should I mess to get more stable DRAM?

When your Memory is stable in MemTest86+ and you still have stability problems in your OS, it's possible that the problem isn't your Memory but something else. That's why I say that you should try the CPU and NB Clock Skew.

[Alien Grey]

You have your sticks in A1/B1 or A2/B2?

And did you change it manually or it was in MEM SPD? What tREF do you have? Or maybe could you screenshot Everest Chipset info?

I use A1 and B1 for my Memory.

I don't change tREF it's at the default 3120T. I didn't try it with changing tREF because the ASUS Tech Support thinks that you don't need to change it.

Is this one of the problems that it randomly fails with the Memory running at DDR +1200MHz?

I don't know. This is something that the ASUS Tech Support should try to find out because I can't change it in the BIOS.
The problem that it randomly fails is probably something with the DRAM Clock Fine Delays or something that changes, where we don't have control over in the BIOS, when we change the DRAM CLK Skew on Channel A/B. If you change the DRAM CLK Skew on Channel A/B you can have similar random failures in Prime95. But who am I to say that this is probably causing the random failures with the Memory at DDR +1200MHz.

You can see what the timings are for my G.SKILL F2-9600CL5D-4GBPI. This is with DRAM Timing Control on Auto in the BIOS.

[RedBull1985]

How can the DIMM CLock Fine Delays be adjusted?

[kuebk]

So I did it.

Finally I've achieved 600mhz on ram, the problem was as I previously supposed based in my MEM.
Good that I have 2 pairs of 2x1 kit, changed to 2nd one and bang. Worked as a charm on previous settings.



Probably can go lower with volts on MCH/DDR but that will require more time.

[kuebk]

How can the DIMM CLock Fine Delays be adjusted?

Use CLK Skews in bios.

[Alien Grey]

So I did it.

Finally I've achieved 600mhz on ram, the problem was as I previously supposed based in my MEM.
Good that I have 2 pairs of 2x1 kit, changed to 2nd one and bang. Worked as a charm on previous settings.

Probably can go lower with volts on MCH/DDR but that will require more time.

That's .

Good work.

You can try to lower some voltages now.