Thanks for your replies!
Right now I am having 2-6-2-6T. The 6T belongs to the channel were the sticks are in. I set 200 ps advanced on Dram Clock Fine Delay though. The system seems to be stable.

@mikeyakame,
I am running a PL of 6 by using 1.33v (=1.36 real) on the NB right now (450 MHz fsb@600 MHz ram).
The 1.45v on the NB for a PL of 7 you suggested is probably meant for quadcores,
see http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=9

Well mike there is a question left about reading the Bar_Edt_3.
You told us in your post 2016 a lot about the values in the MCHBAR registers:
CH1 Clock Drive Strength = Offset 33Dh, Dimm1 Clock Drive = 33Dh[3:0], Dimm2 Clock Drive = 33Dh[7:4]

Clock Drive = 3,
FED14330 00000000 00CC0000 02000000 00003300

Clock Drive = 5,
FED14330 00000000 01540000 02000000 00005500

CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]

I am able to find the base adress register FED14330. I see the number 00006600 in the 4th column 0C.
But I cannot find the clock drive = 5 CH1 DQ (data) ...
Where the hell is that address hidden?