X48 Rampage Formula Preview.

[mikeyakame]

No, I don't know that. The only thing I know is that if you leave it on auto the BIOS calculates the DRAM Clock Fine Delays and it's seems to be working stable like that.

If auto gives those values something isn't working right, loosen up Performance level and see if they change.

Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low.

For Example, I'll see

Dimm2 Fine Control Delay = 9T (868ps)
Dimm1 Fine Control Delay = 8T (786ps)
Ch1 Fine Command Delay = 9T (868ps)
Dimm4 Fine Control Delay = 1T (39ps)
Dimm3 Fine Control Delay = 9T (878ps)
Ch2 Fine Command Delay = 0T (0ps)

That means detection was corrupted.

Dimm4 Fine Control Delay = AT (10T) (962ps)
Ch2 Fine Command Delay = AT (10T) (962ps)

Is how it appears when it detects correctly.

You won't read these values without looking at MCHBAR registers, I have the PS values displayed in bios though and that is what the registers are set to when I check them.

Anyway they aren;t Fine Clock Delay but they give you an idea of what I'm talking about.

I don't know exactly if your ICs require 600+ps fine clock delay (which is 10T), hell they might but I've seen only Micron IC's ever need this much, not ProMOS like used in the 9600s.

With Powerchip ICs like used on the G.Skill PI 8500/8800s my 8800s use:

Dimm1 Fine Clock Delay 1768ps (10T)
Dimm2 Fine Clock Delay 315ps (4T)
Dimm3 Fine Clock Delay 1796ps (10T)
Dimm4 Fine Clock Delay 345ps (4T)

That is with memory in Dimm2/Dimm4. Dimm1/3 autodetect so high because they are empty, so their value is cross channel delay of 28ps + timeout which gives 1768ps for timeout.