O.K.
@Mike,
you told me: "Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low".
Does that mean I should rise up my vNB and I´ll have a change to reduce the DRAM Clock Fine Delay???
Where can I find "CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]" in BAR_Edit_§?

@Alien Grey,
I asked Felix if he´s going to fix Memset4 for working on Windows 7 in the New Memory Tweaker for Intel Chipsets thread but I haven´t got an answere up to now.