X48 Rampage Formula Preview.

[Fritz_the_germ]

Hi folks!
I just changed my bios settings you can see below and after the POST I had a black sreen that says:
"The file is possibly corrupt. The file header checksum does not match the computed checksum".
These were the bios settings that my system wouldn´t accept:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [460]
FSB Strap to North Bridge [333]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1226 MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [6]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1.30625V]
CPU PLL Voltage [1.54V]
North Bridge Voltage [1.33V=1.36V real]
DRAM Voltage [1.80V=1.89V real]
FSB Termination Voltage [1.24V=1.16Vreal]
South Bridge Voltage [1.05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

When I set fsb to 456 MHz the system starts just fine.

There is another thing that bothers me. My DRAM Clock Fine Dealy is 10T to each channel. Sometimes it helps setting more Dram Clock Skew to "advanced" sometimes it doesn´t.
So I wonder why my system won´t work with a fsb at 460 MHz and how I am able to reduce the Dram Clock fine Delay permanently.