X48 Rampage Formula Preview.

[Alien Grey]

Hi folks!
I´m planung to do the "pencil mod" because my system isn´t stable when I set LLC disabled. To enable the LLC makes to system stable but I am afraid to demage the 45nm cpu for 24/7 setting.
Isn´t the sens of the LLC to prevent short time high voltages?
Does anybody has experiences having done to "pencil mod"?


How can I´ll be Xtreme Member?

Your CPU isn't going to die because you use LLC.

You need more posts to become Xtreme Member.

[Snyxxx]

Ok, just picked up two of these boards that will be watercooled.

I use DDR-1000 4-4-4-15 OCZ VX2s and noticed that I can set the BIOS (803) to a Command Rate of 1N (I assume is 1T), but this setting does not stick in windows as confirmed by Everest and CPU-Z. It shows as 2T always.

Anyone else see this issue. I also saw it in BIOS 603 that came with the board. I was hoping BIOS 803 would fix it, but it did not.

Thanks.

[Alien Grey]

Ok, just picked up two of these boards that will be watercooled.

I use DDR-1000 4-4-4-15 OCZ VX2s and noticed that I can set the BIOS (803) to a Command Rate of 1N (I assume is 1T), but this setting does not stick in windows as confirmed by Everest and CPU-Z. It shows as 2T always.

Anyone else see this issue. I also saw it in BIOS 603 that came with the board. I was hoping BIOS 803 would fix it, but it did not.

Thanks.

I've tried that with my OCZ HPC PC2-8500 to run them at 800MHz 4-4-4-12 and 1N with the same results that you are experiencing. It always showed up 2N. I never tried to find out what's the problem.

[Snyxxx]

I've tried that with my OCZ HPC PC2-8500 to run them at 800MHz 4-4-4-12 and 1N with the same results that you are experiencing. It always showed up 2N. I never tried to find out what's the problem.

Thanks for the confirmation. Just wanting to make sure I was not crazy. I knew it would be too good to be true for an intel chipset to run at 1T as they normally do not even have the option and run only at 2T.

[ElAguila]

Anyone running a GTX295 on this mobo?

[Warpcore]

I'm running the 295 and works great.

[Fritz_the_germ]

Hi folks!
I just changed my bios settings you can see below and after the POST I had a black sreen that says:
"The file is possibly corrupt. The file header checksum does not match the computed checksum".
These were the bios settings that my system wouldn´t accept:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [460]
FSB Strap to North Bridge [333]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1226 MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [6]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1.30625V]
CPU PLL Voltage [1.54V]
North Bridge Voltage [1.33V=1.36V real]
DRAM Voltage [1.80V=1.89V real]
FSB Termination Voltage [1.24V=1.16Vreal]
South Bridge Voltage [1.05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

When I set fsb to 456 MHz the system starts just fine.

There is another thing that bothers me. My DRAM Clock Fine Dealy is 10T to each channel. Sometimes it helps setting more Dram Clock Skew to "advanced" sometimes it doesn´t.
So I wonder why my system won´t work with a fsb at 460 MHz and how I am able to reduce the Dram Clock fine Delay permanently.

[Alien Grey]

Hi folks!
I just changed my bios settings you can see below and after the POST I had a black sreen that says:
"The file is possibly corrupt. The file header checksum does not match the computed checksum".
These were the bios settings that my system wouldn´t accept:

Ai Overclock Tuner [Manual]
OC from CPU Level Up [Auto]
CPU Ratio Control [Manual]
Ratio CMOS Setting: [9]

FSB Frequency [460]
FSB Strap to North Bridge [333]
PCIE Frequency [100]

RAM
DRAM Settings [Manual]
DRAM Frequency [1226 MHz]
DRAM Command Rate [2T]
DRAM Timing Control [Manual]
DRAM CMD Skew on Channel A [Auto]
DRAM CMD Skew on Channel B [Auto]
DRAM Clock Skew on Channel A [advanced 100ps]
DRAM Clock Skew on Channel B [advanced 100ps]

CAS# Latency [5]
RAS# to CAS Delay [5]
RAS# Precharge [5]
RAS# Active Time [15]
RAS# to Ras# Delay [Auto]
Row Refresh Cycle Time [Auto]
Write Recovery Time [Auto]
Read to Precharge Time [Auto]
Read to Write Delay (S/D) [Auto]
Write to Read Delay (S) [Auto]
Write to Read Delay (D) [Auto]
Read to Read Delay (S) [Auto]
Read to Read Delay (D) [Auto]
Write to Write Delay(S) [Auto]
Write to Write Delay (D) [Auto]

DRAM Static Read Control [Enabled]
Ai Clock Twister [moderate]
Transaction Booster [Manual]
Common Performance-Level [7]
Pull-In CHA PH1 [deaktiviert]
Pull-In CHA PH2 [deaktiviert]
Pull-In CHA PH3 [deaktiviert]
Pull-In CHB PH1 [deaktiviert]
Pull-In CHB PH2 [deaktiviert]
Pull-In CHB PH3 [deaktiviert]

Voltage Settings
CPU Voltage [1.30625V]
CPU PLL Voltage [1.54V]
North Bridge Voltage [1.33V=1.36V real]
DRAM Voltage [1.80V=1.89V real]
FSB Termination Voltage [1.24V=1.16Vreal]
South Bridge Voltage [1.05V]
Loadline Calibration [Enabled]

CPU GTL Reference [0,63x]
North Bridge GTL Reference [0.67x]
DDR2 Channel A REF Voltage [Auto]
DDR2 Channel B REF Voltage [Auto]
DDR2 Controller REF Voltage [Auto]
SB 1.5V Voltage [Auto]
CPU Clock Skew [Delay 100ps]
NB Clock Skew [normal]

When I set fsb to 456 MHz the system starts just fine.

There is another thing that bothers me. My DRAM Clock Fine Dealy is 10T to each channel. Sometimes it helps setting more Dram Clock Skew to "advanced" sometimes it doesn´t.
So I wonder why my system won´t oc to a fsb of 460 MHz and how I am able to reduce the Dram Clock fine Delay permanently.

For FSB > 450MHz you need higher FSB Termination Voltage and higher NB Voltage.

DRAM Clock Fine Delays around 10T are fine for memory speed >= 1200MHz.

[Fritz_the_germ]

Thank you Alien Grey!
I trust you telling me Dram Clock Fine Delays around 10T are fine for a memory speed of 1200 MHz
Do you know how a to calculate that ?

[mikeyakame]

For PL7 you need upwards of 1.45v Vnb.

[Alien Grey]

Thank you Alien Grey!
I trust you telling me Dram Clock Fine Delays around 10T are fine for a memory speed of 1200 MHz
Do you know how a to calculate that ?

No, I don't know that. The only thing I know is that if you leave it on auto the BIOS calculates the DRAM Clock Fine Delays and it's seems to be working stable like that.

[mikeyakame]

No, I don't know that. The only thing I know is that if you leave it on auto the BIOS calculates the DRAM Clock Fine Delays and it's seems to be working stable like that.

If auto gives those values something isn't working right, loosen up Performance level and see if they change.

Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low.

For Example, I'll see

Dimm2 Fine Control Delay = 9T (868ps)
Dimm1 Fine Control Delay = 8T (786ps)
Ch1 Fine Command Delay = 9T (868ps)
Dimm4 Fine Control Delay = 1T (39ps)
Dimm3 Fine Control Delay = 9T (878ps)
Ch2 Fine Command Delay = 0T (0ps)

That means detection was corrupted.

Dimm4 Fine Control Delay = AT (10T) (962ps)
Ch2 Fine Command Delay = AT (10T) (962ps)

Is how it appears when it detects correctly.

You won't read these values without looking at MCHBAR registers, I have the PS values displayed in bios though and that is what the registers are set to when I check them.

Anyway they aren;t Fine Clock Delay but they give you an idea of what I'm talking about.

I don't know exactly if your ICs require 600+ps fine clock delay (which is 10T), hell they might but I've seen only Micron IC's ever need this much, not ProMOS like used in the 9600s.

With Powerchip ICs like used on the G.Skill PI 8500/8800s my 8800s use:

Dimm1 Fine Clock Delay 1768ps (10T)
Dimm2 Fine Clock Delay 315ps (4T)
Dimm3 Fine Clock Delay 1796ps (10T)
Dimm4 Fine Clock Delay 345ps (4T)

That is with memory in Dimm2/Dimm4. Dimm1/3 autodetect so high because they are empty, so their value is cross channel delay of 28ps + timeout which gives 1768ps for timeout.

[Alien Grey]

If auto gives those values something isn't working right, loosen up Performance level and see if they change.

Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low.

For Example, I'll see

Dimm2 Fine Control Delay = 9T (868ps)
Dimm1 Fine Control Delay = 8T (786ps)
Ch1 Fine Command Delay = 9T (868ps)
Dimm4 Fine Control Delay = 1T (39ps)
Dimm3 Fine Control Delay = 9T (878ps)
Ch2 Fine Command Delay = 0T (0ps)

That means detection was corrupted.

Dimm4 Fine Control Delay = AT (10T) (962ps)
Ch2 Fine Command Delay = AT (10T) (962ps)

Is how it appears when it detects correctly.

You won't read these values without looking at MCHBAR registers, I have the PS values displayed in bios though and that is what the registers are set to when I check them.

Anyway they aren;t Fine Clock Delay but they give you an idea of what I'm talking about.

I don't know exactly if your ICs require 600+ps fine clock delay (which is 10T), hell they might but I've seen only Micron IC's ever need this much, not ProMOS like used in the 9600s.

With Powerchip ICs like used on the G.Skill PI 8500/8800s my 8800s use:

Dimm1 Fine Clock Delay 1768ps (10T)
Dimm2 Fine Clock Delay 315ps (4T)
Dimm3 Fine Clock Delay 1796ps (10T)
Dimm4 Fine Clock Delay 345ps (4T)

That is with memory in Dimm2/Dimm4. Dimm1/3 autodetect so high because they are empty, so their value is cross channel delay of 28ps + timeout which gives 1768ps for timeout.

I know it's strange with the high DRAM Clock Fine Delays. It actually works stable with that high delays. Advancing the delays makes it unstable.

With the G.Skill F2-9600 at 1140MHz in slots A1 and B1, I need 4T.

[Fritz_the_germ]

Thanks for your replies!
Right now I am having 2-6-2-6T. The 6T belongs to the channel were the sticks are in. I set 200 ps advanced on Dram Clock Fine Delay though. The system seems to be stable.

@mikeyakame,
I am running a PL of 6 by using 1.33v (=1.36 real) on the NB right now (450 MHz fsb@600 MHz ram).
The 1.45v on the NB for a PL of 7 you suggested is probably meant for quadcores,
see http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=9

Well mike there is a question left about reading the Bar_Edt_3.
You told us in your post 2016 a lot about the values in the MCHBAR registers:
CH1 Clock Drive Strength = Offset 33Dh, Dimm1 Clock Drive = 33Dh[3:0], Dimm2 Clock Drive = 33Dh[7:4]

Clock Drive = 3,
FED14330 00000000 00CC0000 02000000 00003300

Clock Drive = 5,
FED14330 00000000 01540000 02000000 00005500

CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]

I am able to find the base adress register FED14330. I see the number 00006600 in the 4th column 0C.
But I cannot find the clock drive = 5 CH1 DQ (data) ...
Where the hell is that address hidden?

[Alien Grey]

Thanks for your replies!
Right now I am having 2-6-2-6T. The 6T belongs to the channel were the sticks are in. I set 200 ps advanced on Dram Clock Fine Delay though. The system seems to be stable.

@mikeyakame,
I am running a PL of 6 by using 1.33v (=1.36 real) on the NB right now (450 MHz fsb@600 MHz ram).
The 1.45v on the NB for a PL of 7 you suggested is probably meant for quadcores,
see http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=9

Well mike there is a question left about reading the Bar_Edt_3.
You told us in your post 2016 a lot about the values in the MCHBAR registers:
CH1 Clock Drive Strength = Offset 33Dh, Dimm1 Clock Drive = 33Dh[3:0], Dimm2 Clock Drive = 33Dh[7:4]

Clock Drive = 3,
FED14330 00000000 00CC0000 02000000 00003300

Clock Drive = 5,
FED14330 00000000 01540000 02000000 00005500

CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]

I am able to find the base adress register FED14330. I see the number 00006600 in the 4th column 0C.
But I cannot find the clock drive = 5 CH1 DQ (data) ...
Where the hell is that address hidden?

The NB Voltage around 1.45V is for FSB > 450MHz.

[Fritz_the_germ]

O.K.
@Mike,
you told me: "Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low".
Does that mean I should rise up my vNB and I´ll have a change to reduce the DRAM Clock Fine Delay???
Where can I find "CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]" in BAR_Edit_§?

@Alien Grey,
I asked Felix if he´s going to fix Memset4 for working on Windows 7 in the New Memory Tweaker for Intel Chipsets thread but I haven´t got an answere up to now.

[Alien Grey]

O.K.
@Mike,
you told me: "Only time I've seen that kind of behaviour on this DFI board is when PL is too tight and NB voltage is too low".
Does that mean I should rise up my vNB and I´ll have a change to reduce the DRAM Clock Fine Delay???
Where can I find "CH1 DQ (data) Drive Strength = Offset 419h, Dimm 1 DQ Drive = 419h[3:0], Dimm2 DQ Drive = 419h[7:4]" in BAR_Edit_§?

@Alien Grey,
I asked Felix if he´s going to fix Memset4 for working on Windows 7 in the New Memory Tweaker for Intel Chipsets thread but I haven´t got an answere up to now.

If you look a few posts back in the thread you'll see that there is a lot he can change in MemSet but he doesn't have the time to do it.

[Fritz_the_germ]

My quest is embarrassing because Felix has nothing to do but I. I had to change the display setting to the default text size. Sorry for that...

[Alien Grey]

A lot of information is lost.

[screwtech02]

Yeah, this is another "backup" of the forums.... Seems that "overclockers forums" is a bit more "stable" place to post as of late....

[Grnfinger]

Well now, how do you lose information upgrading ram????

[screwtech02]

Well now, how do you lose information upgrading ram????

[situman]

Yeah, this is another "backup" of the forums.... Seems that "overclockers forums" is a bit more "stable" place to post as of late....

People actually post over there?

[Alien Grey]

Well now, how do you lose information upgrading ram????

I don't know. Maybe they clocked the server to high.

I suggest that if you post something on the forum that you keep a backup of your post somewhere in case the information gets lost again.

[screwtech02]

People actually post over there?

I would have to assume so, have seen alot of XS people over there when this site is down....