Uhm I'm not exactly getting what you are saying.
Are you saying that the NMOS driver current of 1354μA/μm on AMD's 45 nm. process is the same as on Intel's 45 nm. HKMG process, even though AMD's process does not use HKMG? Or is that NMOS driver current of AMD's 45 nm. process the same as what Intel would get if they had a 45 nm. process that did not use HK materials and metal gates? I'm guessing the former....
Could it be that their C3 revision of Shanghai and Deneb will implement these optimizations? That could explain the lower TDPs on their AM3 Deneb chips.





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