Originally Posted by
IEDM-2008
27.7 Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS
Technologies for High Performance Microprocessors,
J. Hoentschel, A. Wei, M. Wiatr, A. Gehring, T.
Scheiper, R. Mulfinger, T. Feudel, T. Lingner, A. Poock, S. Muehle, C. Krueger, T. Hermann*, W. Klix*,
R. Stenzel*, R. Stephan, P. Huebler, T. Kammler, P. Shi, M. Raab, D. Greenlaw, M. Horstmann, AMD
Fab 36 LLC & Co. KG, *University of Applied Science Dresden
Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leadingedge
65nm and 45nm PD-SOI CMOS technologies. The asymmetric NMOS and PMOS saturation drive
currents improve up to 12% and 10%, respectively, resulting in performance of NIDSAT=1354μA/μm and
PIDSAT=857μA/μm. Product-level implementation show a speed benefit of 12%.
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