
Originally Posted by
rob2k
This is my first Intel and DDR3 system after many years of AMD and DDR2 so anyone please correct me if I'm wrong. The FSB freq is quad pumped so 4x the bus speed where the divider is the FSB to DRAM ratio so half of the effective FSB freq with the 1:2 divider. Then with DDR memory (DDR=Double Data Rate) the memory speed is multiplied by 2 for it's effective frequency which then equals the FSB freq (so yes 1:1 there). By using another divider the memory can be ran slower - and more recently faster (asynchronously). Usually running components synchronously yields better performance. Think of the divider as the fraction of the FSB frequency but then double that result for the memory frequency. Hope i've not made a hash of that and i'm not teaching you how to suck eggs (as the saying goes!). What you have in mind sounds fine and perfectly achievable after binning the HPA.
The 2x1Gb configuration in the white sockets seems to be the most clockable on this board.
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