Quote Originally Posted by [XC] Lead Head View Post
Just because a process is smaller does not make it more advanced. Theres a reason why ATI's and nVidias 600MHz chips used 120+ watts of power, while AMDs and Intel's 2.4+ GHz chips only use <75 watts, and as of lately, the transistor counts are similar as well.

What are you talking about? I don't see any AMD chips randomly dieing. I've seen plenty of nVidia and ATI GPUs die all of a sudden, however.

The only variances in AMD's CPUs is their weekly steppings, which is done to refine the process for better power usage at the designed frequencies. Boohoo if one stepping can't overclock better then another, that has nothing to do with quality control.

AMD's chip process is among some of the most advanced in the world, not many fabs have the capability to make changes to the process on the fly like AMD can. AMD actually had to send over some of their software and hardware in order for chartered to be able to produce their CPUs and be able to have weekly steppings.

AMD and IBM work together to develop technologies. Copper interconnects and SOI come to mind.

TSMC's processes are not advanced in anyway, like it was said, they are a very generic process. If they had the refinement like Intel and AMD did, you can bet that GPUs wouldn't be using near the amount of power they are right now, especially at the clocks they are running
Smaller geometry is more advanced, doesn't matter how you cut it. Otherwise everyone would just be pumping out chips in 32nm/22nm right now. The investments in equipments, the tuning on OPC recipes, etc are much harder than you asssumed. If making transistors smaller is such a no-brainer as you suggested, we wouldn't have a 18-24 months cycle for die-shrinks.

GPUs just have poor power consumption designs compare to CPUs; it was never the priority compare to chips used for cell-phones or gadgets. The memory access methodology is so far behind (and very high power consumption) that Nvidia has a hard time getting traction in cell phones compare to Imagination Tech. AFAIK, one of the biggest downfalls/drawbacks of Nvidia's design has been memory bus usage where it has to regularly going out of local cache to fetch data.

TSMC process is *NOT* generic as you believed. As I stated above, they have a process dedicated for low power and a process for higher performance logic. They have not dedicated a lot of efforts at high performance logic due to the lack of volumes (Nvidia and ATI volumes are small); they have dedicated a lot of efforts on low power for high volume customers such as Qualcomm, TI, Broadcom, etc.

Their high performance logic process do need work; it is usually 6-months later than their low power process and yields are usually sub par (partly due to larger die size from Nvidia, ATI and Altera).

Quote Originally Posted by savantu View Post
As a matter of fact Intel does flash on its older FABs ( n-1 and n-2 ).As I've said it is a matter of marring the process to the design.
Intel typically goes for the highest performance possible for its transistors , as a result others generally manage to outpace them in cell density at a given process node.

That's highly unlikely IMO.At best , AMD could get some lines inside a FAB , they need the newest process anyway.And it's a problem of capacity.

I must say I'm extremely surprised at TSMC going SOI for AMD; I thought if anything it will mean AMD transitioning some of its CPU products to bulk.
Intel is transitioning out of the n-2 fab filler strategy (n-1 is mostly used for chipsets) because the transistor designs do not fit well with smaller geometries. As witnessed with their JV with Micron for NAND and ST Micro for NOR.

If Spansion could get a dedicated fab, AMD is very likely to get a dedicated fab if it can committee enough volume.

TSMC going SOI has been speculated for well more than 5 years now (and has been 'evaluating' SOI for the said amount of time).