Quote Originally Posted by GoThr3k View Post
Altough you have some point there shintai, but let's put some thing into consideration

3. The high density part is a typo i think, but high leakage may result to low yields. If you want your semiconductor device to have a maximum TDP of X, and because of the leakage you get a TDP of X+15 on some part, you will have to throw that part away.

4. Maybe optimizing a few nodes in that process line isnt that difficult as you think? it's not because they would have to build CPU's the would have to built new clean rooms or an entire new production line....

Bulk vs SOI => you dont need anything to retool in your fab, only wafers change

High leakage= low HIGH performance yields with high power requirements. But your yields for what they make most of TSMCs customer base its very good. So the only bad parts would be highend GPUs and such. Same reason TSMC launches its low power process first. Generel Purpose process got low priority.

Optimizing a few nodes=redo your entire research, change of tools etc. Its not tweaking later on. Its the basics its wrong with. Its like halfway reinventing your nodetype.

Wafers aint the only thing that change.