AMD turns TSMC into a CPU manufacturing giant

[vitaminc]

You fail to understand companies with their own fabs can DESIGN aswell as optimize for a process THEY control. Same reason Intel says Nehalem will be the first chip to really exploit their 45nm process. Its designed for it. 45nm Core 2 aint.

Don't need to rephrase what I said. In case you didn't catch the bold line in my previous post, here it is again: IDM will always have better process and design integration than fabless.

1. TSMC is the biggest one. But look on their revenue. They have the same revenue as Intel got in 1 single quarter. And having a profit that cant even build 1 45nm factory per year. Yet TSMC produce over 10 times the amount of wafers. TSMC dont make many 45nm chips yet you know. TSMC makes cheap discount chips on a cheap discount process. Thats how their business works and what their consumers want.

I guess that's the reason why AMD can't compete because it has lower revenue than TSMC and much less profitable at the same time.

So what was your point? AMD should stay in IDM model compete against Intel in both process technology and design? Makes so much sense when it can't even rival TSMC for both revenue/profit.

2. DRAM is a multitude different business. It makes absolutely no sense what you write. Intel/AMD could make some very expensive very high performance memory in very low quantities. The businessplan would be what? DRAM production lines are simple and extremely cheap in a ultra low profit market.

You meant I made absolutely no sense because Intel started its business making DRAMs, got almost wiped out by other 'cheap' and 'low cost' manufacturers, and found nirvana in their single IBM design win?

Last time I checked, Samsung's 2008 semiconductor CapEx is $8.3Bn but Intel's CapEx is $5.2Bn. So much for extremely cheap and simiple production lines!!! Unless my math or data goes wrong somewhere but $8.3Bn is more than $5.2Bn.

3. High density leads to low yields? No. Low leakage to low yields? No. I think you mix things up greatly in lack of understanding who they make chips for.

High density => higher errors from OPC (and use of immersion), which leads to lower initial yields, assuming the same die size. Low leakage = wider gates = lower yield, assuming the same transistor count. Low leakage using SOI = higher inherent defects from SOI poly = lower yields.

However, those are initial yields and will be improved as the process matures.

4. So TSMC should use half their profits so AMD can use 5% or less of all their manufactoring lines to make what and for what huge profit? You got even less business knowledge than Hector.

Oh, and remember it would be BULK and not SOI. And AMD would have to respin and redesign large parts of their chips.

Or AMD could loan out some of its IP to TSMC for a dedicated production line. There are a lot of different opportunities if you learn to permutate.

Oh and btw, stop that BULK vs. SOI marketing bullcrap. Intel's 'BULK' is as much different from TSMC's BULK as from AMD's SOI. Charter's BULK/SOI and UMC's BULK are all different too. OPC models for all fabs are all different. But I guess you believe that you can take a GDS2 layout to both TSMC and UMC and expect the same chip spinning out of fabs!!!

High leakage= low HIGH performance yields with high power requirements. But your yields for what they make most of TSMCs customer base its very good. So the only bad parts would be highend GPUs and such. Same reason TSMC launches its low power process first. Generel Purpose process got low priority.

uh, have I not already stated that there's not enough demand from TSMC's customers for high performance node for it to develop the process? Qualcomm, TI and Broadcom/Marvell are much higher volume customers than, say, Altera and Nvidia...