AMD's 3GHz K10 to break 30,000 3DMark06 (Inq)

[Movieman]

If you have those systems, do some benches and publish the results here. It will be highly appreciated and will increase your credibility here.

Would you take my word that he's credible?

[informal]

I think he wouldn't MM .But nice you came forward and said it

[Donnie27]

AMD Phenom X4 can do 3GHz and above

http://my.ocworkbench.com/bbs/showth...200#post420200

Bluetooth is one of those guys who is credible and who got the one of the 1st GA RD790 mobos to test.So this is very good news coming from them!

Note he says air cooling is used and it's a X4 ,so all of the cores must work at the same clock since something is wrong(bios?) and they can't use separate PLLs to clock the cores individually.

And a note to Donnie27 and others going OT in this thread ,for the Nth time:

"Please post something that has to do with Phenom or get out from this news thread!"

We don't need trolling about 4x4 here Donnie.You take your views to separate thread in general hardware and discuss till there is no tomorrow,ok?Or you are afraid it will go down the tubes like the one topic you tried to post recently:"4x4 vs V8"?That was a funny thread,with wrong title,wrong link and wrong posts

The only troll here is YOU! It was an A & B conversation, why don't you C your AMD troll a$$ out of it LOL!? He keeps asking why I called you a Fanboy, sheesh the answer is plain enough.

When Victor, Fugger or Hell, even Movie Man gets a Barkie, I'll believe benchmarks, the rest I'll read but take with a Grain of Salt. Sorry, I can't take pics of the Servers, MACs or the brain-scan machines at work LOL!

[Donnie27]

Would you take my word that he's credible?

[OT]
Yet, he still doesn't know what I do, what I've played with or built My personal stuff has little to nothing do with what servers I've seen, played with or fixed. I do believe he has those even before you spoke up. Yes, your word is more than good enough for me, thanks for backing him up. I'm not running a Server in my home. But I do have two AMD based rigs and two Intel based rigs.

I'm not always right and when proven wrong I'd rather see it as something as learned instead of digging a deeper hole like some others here. So maybe informal is still smarting from being shown the definition of a Paper Launch or the other guy about how much money AMD pays IBM, hell, I don't know. I don't hold grudes.[/OT]

If the 3GHz Barkie did break 30K on 3DBung-O-Marks, big deal since that doesn't translate or carry-over to any real-world Game/s or Apps. Most of the local IT geeks I know aren't excited about Barkie at all (or the next Intel Xeon). Most just say, we'll see and go from there. These men and women are saying sales will be tough/slow going for Intel and AMD. I asked why and each said "Glut". Now it is Funny as hell that I can say both and certain folks read that as AMD bashing

[informal]

Sure thing Donnie,lmao.I am a "troll" because i post relevant news in connection to the topic title,and you are a great dude who posts anything that is off topic in a news thread.News flash for you:this is a news thread!Get it!? Maybe not...Too hard to figure i guess.

And Donnie,I see you still use that bad mouth to label others("troll a$$" for instance).I wonder how much more will the mod on duty here keep his eyes shut or half open.After all we are in a news thread where people come to read news.Not off topic arguments about non related stuff.They can read that at other subforums(or that's the way it should be..)

[njkid32]

Guys I'm going to say this once and if nobody listens or I see one more flame this thread is gone and warnings/bans will be handed out.

STOP FIGHTING!

[CraptacularOne]

A few more days, then we'll know what's what fellas.

[informal]

New info from Gary@AnandTech:

Throughout the entire prototype and pre-production (as stated in my last message) process, certain features on the CPU, in the BIOS, or on the chipsets have been turned off/on, latencies have changed, etc, etc. This is a normal part of the engineering process as the design is fleshed out and finalized. It does not represent final silicon capabilities and performance.


As I said earlier, I used a poor example as it was not meant to be taken literally spec for spec when comparing engines and CPUs. Regardless of the example, the point was that the platform performance improved significantly as the core speeds improved and this included performance per watt among other indicators. There is a myriad of reasons as to why this occured but considering the early silicon, BIOS, and chipset designs, we could only speculate as to why and I tried to present a few reasons that we honed in on.

If you compare a B00 chip from May to a B02 today, there is a significant difference in performance in all areas (26 seconds in SuperPI 1m for one) and my comments represent observations of what has occurred over this time period. We have final silicon now and results will be posted in the near future. My observations today are different than they were two weeks ago and as the platform matures they will change again.


Once we see the HT 3.0 capable chipsets and Phenom cores mature then we will have an even better indication of the performance of this core design in the consumer market but for now the initial release is Barcelona in the enterprise market.

So Gary said that the jump in performances between B00s from May to B02s is very large(he saw the time in SPi 1m test decreased by 26s from B00's score-quite a lot).This right there invalidates the coolaler's forum topic(which BTW is gone-at least the pictures of the K10 ES results)

Also he said he saw a visible improvement within the last two weeks ,so this means that a lot of beta silicon chips floats at Far East's mobo factories.
Like he said:"My observations today are different than they were two weeks ago and as the platform matures they will change again." Presumably he is talking about the Phenom and RD790 boards which will be a little late (not September but middle of October-due to low volume of K10 DVTs out there at the moment).
All of this still gives us a hint about a variety of chips,boards and support for them in form of functional bioses.6 days to go and no retail silicon leaked.Tells a lot about NDA and what AMD actually sends to others for testing.

[tictac]

and for the clueless and stay at you're desktop. just check my sig what i am working on. so i do have an idea what is going on in the cpu world.

B0 stepping eh....
early sample?

[dinos22]

ROFL
26s improvement in 1M

something tells me it's still a dog if you can shave off 26seconds in beta

[hollo]

For example Kentsfield/Woodcrest performance is scaling incredibly well, while being a MCM approach, while Pentium EE 840 scales poor, although it is a native dual core.

nay, the pentium d series is MCM, including the EE versions. native should definitely scale a little better, the early k10 benchmarks already show a scaling improvement in cinebench (~6x performance improvement going from 1-8 cores for xeon vs ~7x for k10)

[hipro5]

ROFL
26s improvement in 1M

something tells me it's still a dog if you can shave off 26seconds in beta

[adamsleath]

http://www.tcmagazine.com/comments.php?id=15914&catid=2

AMD's cat, the K10-based Opteron is finally out of the bag as, on September 1st the company has announced that it has already begun shipping the new processors.

[rozzyroz]

Do a little research. Pentium 840EE is the first x86 dual core and it is a native(monolithic die) dual core.

That is due to the direct (CPU to CPU) HTT link VS the parallel indirect (CPU to northbridge to CPU) link. Not because of the native vs MCM approach. Try benching single K10 and single C2Q systems.

840ee is two prescotts on a piece of silicon. http://www.hardwareanalysis.com/content/article/1797/

[Donnie27]

Sure thing Donnie,lmao.I am a "troll" because i post relevant news in connection to the topic title,and you are a great dude who posts anything that is off topic in a news thread.News flash for you:this is a news thread!Get it!? Maybe not...Too hard to figure i guess.

And Donnie,I see you still use that bad mouth to label others("troll a$$" for instance).I wonder how much more will the mod on duty here keep his eyes shut or half open.After all we are in a news thread where people come to read news.Not off topic arguments about non related stuff.They can read that at other subforums(or that's the way it should be..)

So your constant Trolling directed at me is relevant and on Topic, right? Stop acting like a Troll and I'll stop calling you one If I bother you soooooo much there is such a thing as an ignore button.

Six more days to see what Barkie can do. I'll be happy for heart-broken AMD Fans everywhere who've had to put up with Conroe Spankings for how long now? Maybe the forums will be a little more peaceful if Barkie performed anywhere near the 30K rumored by these guys.

[STaRGaZeR]

Then K8 is not a native dual core.

Don´t be a fool. Neither Smithfield or Presler are native dual cores, they are MCMs of Prescott and Cedar Mill.

[Shintai]

Yes IT IS

K8 was developed keeping dual cores in mind, but by the time K8 launched there was no demand for dual core chips, and chips ware pretty big themselves.

But due to the fact K8 was designed to be a dual core, amd launched X2 without the need to develop a new core. Intel couldn't offer a native dual core chip based on netburst simply cause the core was lacking core interconnects interface, even the cores of the monolithic 840EE communicated with each other through the FSB, like the later MCM pendium Ds did.

Native is better in terms of performance, x2 scales better than PentiumD, but chips are larger and yields - lower. MCM is more flexible and probably the better way to do things. I think amd go for the native stuff cause they want to cut development costs. Of course intels approach was lame - using the FSB for core to core communication. AMD could have used HT to make MCM modules and they would have been very close to a native design.

It depends how you define native dualcore. X2 is just 2 totally seperate cores with a shared SRI thats basicly its northbridge. In "nativeness" you would have C2D>CD>X2>Presler>Smithfield.

Also native doesnt mean it scales better by default. A C2D doesnt scale superiour to X2. Tho its just as more native to K8, that K8 is to P4.

[dinos22]

hey george
looks like i'll be able to fend off these new CPUs with a Celeron
http://www.xtremesystems.org/forums/...d.php?t=157673

[kl0012]

But due to the fact K8 was designed to be a dual core, amd launched X2 without the need to develop a new core. Intel couldn't offer a native dual core chip based on netburst simply cause the core was lacking core interconnects interface, even the cores of the monolithic 840EE communicated with each other through the FSB, like the later MCM pendium Ds did.

Actually all intercore communications in x2 K8 goes through the main memory just like in Pentium D.
http://www.xbitlabs.com/articles/cpu...nalysis_4.html
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that!

[Donnie27]

Actually all intercore communications in x2 K8 goes through the main memory just like in Pentium D.
http://www.xbitlabs.com/articles/cpu...nalysis_4.html
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that!

QFT!

Barcelona will connect to an L3 the same same way. Last thing I saw said there wasn't any Core to Core, L1 to L1 or even L2 to L2 interconnections. Each are separate Core that can run without the rest of the system or cores. You can't split a C2D like that. Sure two Cores that make up C2Q is different.

If K10 is faster and IHMO it will be in some apps, it will be faster because of its Core Improvements, not some Native BS. Singled threaded app/s should bare this out. These type apps will shoe the improvement made to each core. The problem is AMD's marketing folks would rather talk Catch Prases since that easier to grasp. IMHO, that's disrespecting the folks who love them. That's like saying our fans are Dumb so let's give them something simple.

[informal]

I see the off topic discussion is going rampant again..Hmm,mods must have a day off

Back on K10 topic.New info is coming out,this time with some AMD slides

Inside AMD K10 Architecture

Some new info from here:
http://www.hardwaresecrets.com/article/480/1

From this page :http://www.hardwaresecrets.com/article/480/5 of the article we have a glimpse of 45nm offerings(all with some new codenames as Suzuka 45nm quad core based on Shangai )

Here is a quick summary of the cores that will be launched for the server market based on K10 architecture:
Barcelona: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 65 nm manufacturing process.
Budapest: dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, conventional DDR2 memory, socket 1207 (socket F), HyperTransport 1.x or 3.0, 65 nm manufacturing process.
Shanghai: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 45 nm manufacturing process.
Montreal: octal- or quad-core Opteron on the 2000 and 8000 series, 1 MB L2 memory cache per core, 6 MB or 12 MB L3 memory cache, registered DDR3 memory, socket G3, HyperTransport 1.x, 45 nm manufacturing process.
Suzuka: quad- or dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, conventional DDR3 memory, socket AM3, HyperTransport 3.0, 45 nm manufacturing process.

From here we can see the uni vs split power plane difference in K10 Barcelona:



Here is a Phenom desktop line up:

Here is a quick summary of the cores that will be launched for the desktop market based on K10 architecture:
Spica: A single-core Sempron LE CPU, with 512 KB L2 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Rana: Dual-core Athlon X2 LS CPU, with 512 KB L2 memory cache per core, L3 memory cache (value not disclaimed) regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Kuma: Dual-core Phenom X2 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Agena: Quad-core Phenom X4 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Agena FX: Quad-core Phenom FX CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+ or socket 1207+.

And finally the roadmap(showing the Dual Core Rana clearly as Stars core and NOT the RevG derivative as some earlier suggested)


Server roadmap:

[savantu]

Don´t be a fool. Neither Smithfield or Presler are native dual cores, they are MCMs of Prescott and Cedar Mill.

Maybe you should do some research before talking out of your south pole....

[savantu]

So the highest clocked K10 would be the 2.4GHz at launch. Well, thats a bad news.

Umh , no.

IIRC the highest part will be 2GHz~95w and higher clocked ones will arrive in Q4 ( nov-dec ).

[informal]

So the highest clocked K10 would be the 2.4GHz at launch. Well, thats a bad news.

First,who said 2.4Ghz will be the launch freq.?And if it is ,why is it a "bad news"?You know how K10 performs,show us the review..

Second,latest informations suggest 2.2Ghz at launch,not 2.4Ghz.The higher clocked versions for servers are due out in late October.

[Shadowmage]

2.4 at launch is certainly better than 2.0 at launch, so I'm happy

Unfortunately that probably won't be enough to beat a 3.33ghz yorkfield