Quote Originally Posted by LOE View Post
But due to the fact K8 was designed to be a dual core, amd launched X2 without the need to develop a new core. Intel couldn't offer a native dual core chip based on netburst simply cause the core was lacking core interconnects interface, even the cores of the monolithic 840EE communicated with each other through the FSB, like the later MCM pendium Ds did.
Actually all intercore communications in x2 K8 goes through the main memory just like in Pentium D.
http://www.xbitlabs.com/articles/cpu...nalysis_4.html
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that!