Quote Originally Posted by mstp2009 View Post
WTF? That's not pwnage you n00b.

It said "The latency to the L3 cache has not been disclosed . . .".

"but it depends on the relative northbridge and core frequencies" simply means THEY DON'T KNOW. Not that it is variable.

Go back and pass your GMAT and then we will talk. Reading comprehension seems to be a problem for you.


We're still waiting on the glorious Reverse Hyperthreading, BTW.
LMAO,you really are cluless,aren't you.And having a nerve to call me a "noob".Sure thing.
Go ahead genius,read the next page:
From a circuit level perspective, the changes between the K8 and Barcelona were extremely significant. Barcelona is specified to operate at a wide range of voltages, from 0.8-1.4V. However, unlike its predecessor, each core in Barcelona has a dedicated clock distribution system (including PLL) and power grid. The frequency for each core is independent of both the other cores, and the various non-core regions; the voltage for all four cores is shared, but separate from the non-core. As a result, power can be aggressively managed by lowering frequency and voltage whenever possible. To support independent clocking and modular design, asynchronous dynamic FIFO buffers are used to communicate between different cores and the northbridge/L3 cache. These FIFOs absorb any global skew or clock rate variation, but the latency for passing through depends on the skew and frequency variance – which is why the L3 cache latency is variable. The northbridge and L3 cache compose roughly 20% of the die and share a voltage and clock domain that is independent of the four cores, which is essential for mobile applications. Previously, the northbridge clock and voltage was tied to the processors, so systems with integrated graphics could not reduce the processor voltage or frequency to deep power saving states. Separate sleep states, voltages and frequencies for the northbridge and processors should lower AMD’s average power dissipation which will help in the mobile market.
Pwnd!