That document says nothing about L3 latency.
Also from this patent:
http://patft.uspto.gov/netacgi/nph-P...y=PN%2F7124236
We can see what AMD might have done in K10's L3 cache.
That document says nothing about L3 latency.
Also from this patent:
http://patft.uspto.gov/netacgi/nph-P...y=PN%2F7124236
We can see what AMD might have done in K10's L3 cache.
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