Quote Originally Posted by informal View Post
That document says nothing about L3 latency.

Also from this patent:
http://patft.uspto.gov/netacgi/nph-P...y=PN%2F7124236

We can see what AMD might have done in K10's L3 cache.
What it DOESN'T say is just as important.

It DOESN'T confirm you assertion that the L3 cache has a variable latency.

And after googling for an hour, there is not a single report to confirm what techarp said. And they didn't list their source (how convenient for you).