Quote Originally Posted by informal View Post
First it's not a souce for sure .
Second AMD never ever mentioned the L3 cache latency in your linked document,so no,they did not say what the value is in that document.
Like i said,no source on your side that disputes my link.
And your link could be written by a 12 yo expressing his OPINION.

MY POINT was that AMD themselves have NOT specified that latency is variable.


Since variable latency would be a significant deviation from current CPU design specs (with questionable if any benefit), the assumption should be made that the L3 cache is a fixed latency (i.e. number of cycles).


But in AMD Fanboi land, anything is possible.

How's that REVERSE Hyperthreading coming along?