K10 Scores starting to surface

[informal]

And your link could be written by a 12 yo expressing his OPINION.

MY POINT was that AMD themselves have NOT specified that latency is variable.


Since variable latency would be a significant deviation from current CPU design specs (with questionable if any benefit), the assumption should be made that the L3 cache is a fixed latency (i.e. number of cycles).


But in AMD Fanboi land, anything is possible.

How's that REVERSE Hyperthreading coming along?

So the techarp quote is not good enough??You still think it was 12 yo kid who wrote it(and not the 12 yo who is disagreeing with it)??

Let's see,would one man named David Kanter,a little older than the supposed techarp kid of 12 years,be a good enough source for you??

Start rolling on that floor and laughing at yourself,as of now:

http://www.realworldtech.com/page.cf...1607033728&p=7

A round-robin algorithm is used to give access to one of the four cores each cycle. The latency to the L3 cache has not been disclosed, but it depends on the relative northbridge and core frequencies – for reasons which we will see later.

I made it in red in case you can't see it from that big avatar...

In gamers terms:pwnd.

Edit:
even more pwng coming along:

From a circuit level perspective, the changes between the K8 and Barcelona were extremely significant. Barcelona is specified to operate at a wide range of voltages, from 0.8-1.4V. However, unlike its predecessor, each core in Barcelona has a dedicated clock distribution system (including PLL) and power grid. The frequency for each core is independent of both the other cores, and the various non-core regions; the voltage for all four cores is shared, but separate from the non-core. As a result, power can be aggressively managed by lowering frequency and voltage whenever possible. To support independent clocking and modular design, asynchronous dynamic FIFO buffers are used to communicate between different cores and the northbridge/L3 cache. These FIFOs absorb any global skew or clock rate variation, but the latency for passing through depends on the skew and frequency variance – which is why the L3 cache latency is variable. The northbridge and L3 cache compose roughly 20% of the die and share a voltage and clock domain that is independent of the four cores, which is essential for mobile applications. Previously, the northbridge clock and voltage was tied to the processors, so systems with integrated graphics could not reduce the processor voltage or frequency to deep power saving states. Separate sleep states, voltages and frequencies for the northbridge and processors should lower AMD’s average power dissipation which will help in the mobile market.