K10 Scores starting to surface

[informal]

ROFL. Right.


Care to share your source?



I'm also calling BS on this one. Please show us a historical example of where a BIOS update provided >5% improvement in performance.

And since you are pretty notorious for not providing sources, please give us your source as well.

Go laugh on the floor at yourself.
http://www.techarp.com/showarticle.a...tno=424&pgno=2

L3 Cache

The Barcelona features a large, shared L3 cache that is at least 2MB in size. This L3 cache will be shared by all cores, whether it's a dual-core or quad-core processor.

This cache is 32-way set associative and is based on a non-inclusive victim cache architecture. The latency for any core to retrieve data from the L3 cache is said to be less than 38 clock cycles. Oddly enough, AMD says the actual latency depends on the clock speed of the south bridge.

Above contains a mistake by techarp(it was supposed to say north bridge,but the point is clear)

[JumpingJack]

Agreed, yet you keep insisting (against the limited evidence) that K10 is going to be a C2Q killer.

While we all hope that is true, if just for the sake of competition, there is no evidence to support that claim. And I believe that is the major beef that people have (unsubstantiated claims).

True -- if there is going to be a competitive Q4 and 2008 we need a good run from K10. There is so much conflicting info from hearsay to leaked benchmarks we are still pretty much in the dark.

[mstp2009]

Go laugh on the floor at yourself.
http://www.techarp.com/showarticle.a...tno=424&pgno=2



Above contains a mistake by techarp(it was supposed to say north bridge,but the point is clear)

That is NOT a mistake by techarp. It is correctly listed as southbridge. Northbridge latency is the IMC latency, and that is constant. Southbridge (i.e. peripheral interconnect) is going to vary depending on the external bus speed.

[JumpingJack]

Go laugh on the floor at yourself.
http://www.techarp.com/showarticle.a...tno=424&pgno=2



Above contains a mistake by techarp(it was supposed to say north bridge,but the point is clear)

Interesting... this is something I had not seen... so AMD is adjusting cycle latency to account for clock in L3.... wow, they are really trying squeeze as much from it as they can....

Latency is a physical manifestation of the design/processing of the chip, it is the time required for the request/read and/or write to complete the job, this is temporally fixed, for worst case the CPU sets that to x number of cycles such that X*period > min time for latency, interesting..... if this is true, then these chips will be difficult to overclock, I wonder if they are giving options to increase the L3 latency in BIOS?

[informal]

Ok so this is fair... but once all is set in stone, BIOS, memory, etc... a 2.6 barcey will be 30% faster than a 2.0 GHz barcey.... that we can agree upon.

Finally ,agreed .

AS for the coolaler dude,the results are very strange.Don't know if he has the DVT,maybe so.But the platform he used is unknown,as well as the bios involved(i remember AnandTech said back in June,that K10 at that point needed some have bios patching in order to work).Fits perfectly with ES that were only for platform testing and not perfomance evaluation.AnandTech even got 2 samples but couldn't get them to even boot the system even after 1 month)

[JumpingJack]

That is NOT a mistake by techarp. It is correctly listed as southbridge. Northbridge latency is the IMC latency, and that is constant. Southbridge (i.e. peripheral interconnect) is going to vary depending on the external bus speed.

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?

[informal]

Latency is a physical manifestation of the design/processing of the chip, it is the time required for the request/read and/or write to complete the job, this is temporally fixed, for worst case the CPU sets that to x number of cycles such that X*period > min time for latency, interesting..... if this is true, then these chips will be difficult to overclock, I wonder if they are giving options to increase the L3 latency in BIOS?

I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?

Nothing,mstp is talking out of his ass

[mstp2009]

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?

Only thing I can think of is that AMD has the L3 cache acting similar to what we see in the snoop filter of the newer Intel server chipsets. Prefetching data from RAM or (possibly) the hard drive?

Neither make much sense, however. As you correctly pointed out, have an adjustable speed (i.e. latency) on the L3 cache would make increasing the clocks on K10 a b!t#@. And there is no easy fix to that except to LOCK the L3 cache back to processor frequency.

[mstp2009]

Nothing,mstp is talking out of his ass

Was that called for?

You are a p r ick.

[JumpingJack]

I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.

Actually, I think the split power plane will make it harder.... but now it is becoming clear, I think TechARP may have misprinted, it makes more sense that the L3 will fix withrepect to the IMC (northbridge) fequency and that will vary with the frequency divider necessary to drive the memory.

In terms of OCability, this may or may not be true.... the details of how AMD has implemented the L3 cache is sketchy now based on your link.... if they are adjusting the number of L3 cycle latency dynamically (as you interpret), this means that they are adjusting to keep the L3 cycle latency at the border edge of the physical time it takes for signalling L3... if this is true, overclocking will crap out the L3 very very early. This is why I wonder if they will provide BIOS writers (or should I say BIOS writers provide us) with the ability to adjust the L3 latency cycles.

[Movieman]

All I know is I want to see AMD come out with a dual socket 8 core system that can kick the crap out of my clovers.
That will accomplish many things:
1) Strengthen AMD's share of the marketplace
2) Force Intel to "work" harder
3)Drop prices for all of us
4)Give the AMD fans something to smile about.
It's been a long year for you guys and I can understand the frustration.
I'm not being sarcastic there, I mean that.

[JumpingJack]

All I know is I want to see AMD come out with a dual socket 8 core system that can kick the crap out of my clovers.
That will accomplish many things:
1) Strengthen AMD's share of the marketplace
2) Force Intel to "work" harder
3)Drop prices for all of us
4)Give the AMD fans something to smile about.
It's been a long year for you guys and I can understand the frustration.
I'm not being sarcastic there, I mean that.

I think everyone can agree with this.

[Donnie27]

All I know is I want to see AMD come out with a dual socket 8 core system that can kick the crap out of my clovers.
That will accomplish many things:
1) Strengthen AMD's share of the marketplace
2) Force Intel to "work" harder
3)Drop prices for all of us
4)Give the AMD fans something to smile about.
It's been a long year for you guys and I can understand the frustration.
I'm not being sarcastic there, I mean that.

QFT!

[Ubermann]

Agree also, but i lost faith.
Intel will get even bigger and AMD wont catch up.
AMD has to go with low price to sell if the cpu isnt performing.
It just look bad..and dark and evil Intel is happy.

[Movieman]

Forgeting all the other points, there is one thing that tends to get overlooked that AMD does that is much better than Intel's solution: cpu placement on a dual socket board.
With the large spacing that AMD uses one can use a top end aftermarket heatsink.
On the intels with just one inch between the sides of the sockets your much more limited..

[JumpingJack]

Forgeting all the other points, there is one thing that tends to get overlooked that AMD does that is much better than Intel's solution: cpu placement on a dual socket board.

This is in general true, but I think Intel did themselves on very good one by keeping 45 nm Penryn family in the same socket, and evidently drop in.... this does not happen often.

[JumpingJack]

I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.

You know what is funny, I pulled this paper out quite a while ago and archived it away.... thinking cool... but had not read it.

http://www.cs.utah.edu/~rajeev/pubs/ieeetoc03.pdf

I just remembered I had it....

[Movieman]

This is in general true, but I think Intel did themselves on very good one by keeping 45 nm Penryn family in the same socket, and evidently drop in.... this does not happen often.

Yes, and I have confirmation that my current SM boards will take the Harpertowns with the current available bios from SM site.
Got that from SM on the phone this week..
I just want them to add another 2 inches between the sockets so we can use some good heatsinks..

[mstp2009]

Here is more info on AMD's cache architecture for K10.

DIRECT from the horse's mouth:
http://developer.amd.com/article_print.jsp?id=173

I would like to point out how the L3 cache works:

Another aspect makes the L3 cache unusual is that it is not fed from memory. Rather, it serves as a spill-over cache for items evicted from the L2 cache. So when the L3 cache loads an item into L1 cache and the cache manager can delete it from the L3 cache, room is created for more spill-over from the L2 cache. Eventually, the data item in the L1 cache will make it back to the L2 cache (when the processor is done with it) and the cycle could repeat itself. However, if the processor should need the item right away, it can find it in the L2 cache, if it has not been pushed back out to the L3 cache-and it would thereby obtain faster turnaround. AMD has not published figures on the latency of data access in the L3 cache, so it's not possible currently to know how much faster.

EDIT - AMD seems to think Anandtech did a GOOD evaluation of the Barcelona cache structure:

A thorough, technical, and very detailed description of the Barcelona chip, by an independent authority AnandTech, contains good coverage of the cache architecture:
http://www.anandtech.com/cpuchipsets...spx?i=2939&p=1

[JumpingJack]

Here is more info on AMD's cache architecture for K10.

DIRECT from the horse's mouth:
http://developer.amd.com/article_print.jsp?id=173

I would like to point out how the L3 cache works:

Nice link, thanks... I will read it. Wow, relatively new.... this is good info.

[informal]

That document says nothing about L3 latency.

Also from this patent:
http://patft.uspto.gov/netacgi/nph-P...y=PN%2F7124236

We can see what AMD might have done in K10's L3 cache.

[mstp2009]

That document says nothing about L3 latency.

Also from this patent:
http://patft.uspto.gov/netacgi/nph-P...y=PN%2F7124236

We can see what AMD might have done in K10's L3 cache.

What it DOESN'T say is just as important.

It DOESN'T confirm you assertion that the L3 cache has a variable latency.

And after googling for an hour, there is not a single report to confirm what techarp said. And they didn't list their source (how convenient for you).

[Thesavage]

I remember reading on aceshardware before the crash they had about the possibilty of changing the L3 frequency in the bios as a tweak and the supposed gains this brought.

[informal]

What it DOESN'T say is just as important.

It DOESN'T confirm you assertion that the L3 cache has a variable latency.

And after googling for an hour, there is not a single report to confirm what techarp said. And they didn't list their source (how convenient for you).

At least i have one source.And like you said yourself,you have ZERO!

And a quick search in your post history shows you backup every bs claim you make with solid proofs.Or not:
http://www.xtremesystems.org/forums/...2&postcount=38

[mstp2009]

At least i have one source.And like you said yourself,you have ZERO!.

Yeah, AMD isn't a souce.