K10 Scores starting to surface

[JumpingJack]

That is NOT a mistake by techarp. It is correctly listed as southbridge. Northbridge latency is the IMC latency, and that is constant. Southbridge (i.e. peripheral interconnect) is going to vary depending on the external bus speed.

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?

[mstp2009]

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?

Only thing I can think of is that AMD has the L3 cache acting similar to what we see in the snoop filter of the newer Intel server chipsets. Prefetching data from RAM or (possibly) the hard drive?

Neither make much sense, however. As you correctly pointed out, have an adjustable speed (i.e. latency) on the L3 cache would make increasing the clocks on K10 a b!t#@. And there is no easy fix to that except to LOCK the L3 cache back to processor frequency.