Quote Originally Posted by informal View Post
Go laugh on the floor at yourself.
http://www.techarp.com/showarticle.a...tno=424&pgno=2



Above contains a mistake by techarp(it was supposed to say north bridge,but the point is clear)
Interesting... this is something I had not seen... so AMD is adjusting cycle latency to account for clock in L3.... wow, they are really trying squeeze as much from it as they can....

Latency is a physical manifestation of the design/processing of the chip, it is the time required for the request/read and/or write to complete the job, this is temporally fixed, for worst case the CPU sets that to x number of cycles such that X*period > min time for latency, interesting..... if this is true, then these chips will be difficult to overclock, I wonder if they are giving options to increase the L3 latency in BIOS?