Quote Originally Posted by JumpingJack View Post

Latency is a physical manifestation of the design/processing of the chip, it is the time required for the request/read and/or write to complete the job, this is temporally fixed, for worst case the CPU sets that to x number of cycles such that X*period > min time for latency, interesting..... if this is true, then these chips will be difficult to overclock, I wonder if they are giving options to increase the L3 latency in BIOS?
I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.

Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?
Nothing,mstp is talking out of his ass