[NEW STUFF] Intel LGA1155

[terrace215]

I just look and giggle but the thing is people dont realize what the truth is even if you type out loud like i did about sandy bridge 6/8c being o so different and tweaked that the 2/4c sandy bridge

But you have not said that the 2/4c sandy bridge is NOT a new, completely reworked microarchitecture, just that the 6/8 has even more (potential) changes.

The semiacc author is practically suggesting that 2/4 is a Westmere core bolted to a new uncore with GPU on die, oh, and, uh, plus AVX... or something.

Even Intel has now publicly said "significant IPC improvement" about the 2/4 parts. I don't think that means AVX.

http://download.intel.com/pressroom/...er_English.pdf

(pages 32,33)

http://news.cnet.com/8301-13924_3-20...orsPicksArea.0



Key points
While Intel Executive Vice President David Perlmutter said he would "not do a deep dive" on Sandy Bridge in his Intel Developer Forum Beijing keynote this week, he did reveal some key points about the architecture.

-More efficient: the central processing unit, or CPU, delivers a "significant improvement in instructions per clock," according to Perlmutter, meaning that it is more efficient at executing tasks.

-Faster on-chip communication: different parts of the chip will talk to each other faster--what Perlmutter called "improved inter-buses."

-Shared memory: on-chip memory called cache is shared between the CPU and graphics processing unit, or GPU.

-GPU now part of CPU: Intel combines the CPU and GPU on the same piece of silicon. According to an unofficial photo of the Sandy Bridge chip from Japanese Web site PC Watch, the GPU takes up roughly 25 percent of the processor's real estate.

-New instructions: Sandy Bridge will be the first chip to support Intel's Advanced Vector Extension (Intel AVX) instructions. AVX accelerates a host of multimedia tasks, including video and audio processing.

-More intelligent overclocking: and, finally, Perlmutter mentioned improved Turbo Boost--which speeds up (i.e., "overclocks") or slows down individual cores to meet processing or power efficiency needs.