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Thread: AMD Zambezi news, info, fans !

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  1. #11
    Registered User
    Join Date
    Feb 2005
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    39
    Quote Originally Posted by drfedja View Post
    Again, I don't think so there is the problem with WT. L1D is WT, WCC is write buffer, and L2 is probably WB. Because of WCC there can be some issues with multiple write out streams. Also, we don't know what is behaviour of WCC when two integer cores writing data. There is probably WCC cache trashing.
    WCC is a joke in the current BD implementation and is not able to catch up with the massive loss that comes from the L1D. The entire caching-system is lowering the performance of the ľarch. The L3 is a non-inclusive victim cache (L2 data are evicted to the L3) with data transfered from L3 to the L1D of the expected core without being copied to the L2. That mean high snoop traffic in order to keep the coherency correct. And snoop traffic is something really unwanted from a bandwidth/performance pov. There is a pardox here : The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

    Quote Originally Posted by AKM View Post
    Bullsh1t.
    Last edited by xsecret; 09-13-2011 at 09:07 AM.
    Doc_TB @ CanardPC.Com (FR)

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