Hans wrote for the K8:
http://chip-architect.com/news/2003_...it_Core.html#3Each Scheduler can launch one ALU and one AGU operation per cycle. The ALU operation may come from one x86 instruction while the AGU operation may come from another.
That is no 1.5, that is 3 ... maybe u missed the fact, that the MacroOps are splitted into µOps at that stage ?




Reply With Quote

Bookmarks