AMD's Bobcat and Bulldozer

[informal]

Why its on the chart?

Sure the forntend remains and is capable of decoding 4+1 instructions, but for singelthread int workload one core only has 2alu/agus.

There is no way bulldozer can fuse the int cores to make it act like a virtual 4alu/agu core, afair even JF denied this in this thread.

There won't be any "fusing" of the cores,that's not possible. But AMD is not disclosing all the details such as ,why they now call the 2 pipelines Agen?There was never in the past such a term in their diagrams.It's has always been AGU and this was paired with 1 ALU,with separate schedulers.Now we have unified scheduler and this new Agen unit ,outside of L/S unit that is also on the diagram(standing separately too).And finally we have 2 additional integer units in the FPU .SO if you want to count it you can say its 2+2+1(2) in terms of integer execution power.

edit: the only "fusing" that may happen is in terms of FPU execution,when one core can use both FMAC units for itself.