Quote Originally Posted by Motiv View Post
Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.
http://www.xbitlabs.com/articles/cpu...0_6.html#sect0

Upon the availability of data, the scheduler may issue one integer operation to ALU and one address operation to AGU from each queue. There can be maximum two simultaneous memory requests. So, up to 3 integer operations and 2 memory operations (64-bit read/write in any combination) may be issue for execution per clock. Micro-operations from various arithmetic MOPs are issued for execution from their queues in an out-of-order manner, depending on the readiness of the data.