Well the L1 and L2 latencies look like a good starting point.Originally Posted by danielkza
Then looking at the decode stage, it seems like a bad design to share anything past the Microcode.
The ALUs seem to be starving if you ask me.
Well the L1 and L2 latencies look like a good starting point.
Then looking at the decode stage, it seems like a bad design to share anything past the Microcode.
The ALUs seem to be starving if you ask me.
Fast computers breed slow, lazy programmers
The price of reliability is the pursuit of the utmost simplicity. It is a price which the very rich find most hard to pay.
http://www.lighterra.com/papers/modernmicroprocessors/
Modern Ram, makes an old overclocker miss BH-5 and the fun it was
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