Intel plans to deliberately limit Sandy Bridge overclocking

[informal]

Hmm theres something wrong with that picture, cause it lsts SB with 2mb, yet its either 1.5mb or 2.5mb l3 per core.

Maybe explanation by Hans here:

The total L3 cache is really 8MB but 1/2 MB of each core is reserved for the GPU:

You can see the 5 identical interfaces to the L3 cache ring. The leftmost is the GPU
interface. At the right there is a 6th somewhat different ring interface to the IMU

you must have really good eyes if you can see the SSE and AVX units.

it's easier to claim double pumping like you have but do you realize that the logic required to reach those clock speeds would be 50% more and use 3-10x more power? also did you know that RTL code cant even reach those clocks so you have to custom design millions of transistors?

I just countered your "greatly increased die area" comment with an actual hard data.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.