Quote Originally Posted by qcmadness View Post
I don't have the DDR-3 platform right now, but if you use Everest Memory test, you can get about 10GB/s for L3 cache on Deneb.



It would be the design of the L3 / IMC.

In K8 architecture, IMC directly communicates with L2 cache in each core.
The simple illustration is the CnQ-throttled CPUs have lower memory speed.

In K10 architecture, IMC communicates with L3 cache (or NB?) and the bandwidth is limited to NB frequency.
http://www.xbitlabs.com/articles/cpu...0_8.html#sect4
it never touches the memory controller, its been that way for like 15 years! iirc dual independent buses were on pentium 2. a memory controller is basically like a server/client network that is used for DRAM only. it runs at the same frequency as the DRAM clockspeed. the whole idea of L3 cache is so cores can communicate with out touching mem controller or main memory. as far as bandwidth goes it should be around 50GB/s with significantly lower latency.