Dresdenboys' blog: AMD Bulldozer - Patent based research part 2

[informal]

The problem is the design of L3 cache.

Since L3 cache is slower than dual-channel DDR-3, memory bandwidth is limited to L3 cache speed.

Are you sure L3 in Deneb is slower than DC DDR3 ? That doesn't seem right. The L3 is in Deneb and Agena has a lot lower latency than any possible DDR3 DC configuration you can think of(think ~7ns for the L3 Vs 45ns in the bet case for OCed DDR3 DC on crack...). BW is another matter,the cores does not need that much bandwidth to begin with. Maybe with 8 BD cores we might see a limitation when all the cores are loaded in some mem. BW limited application.