Dresdenboys' blog: AMD Bulldozer - Patent based research part 2

[informal]

Running a taskmaster demo gives away nothing to the competition, it just lets investors and interested parties know that schedules are not slipping.

Why do you think they "showed off" the current state of the Barcelona design at the end of 2006?

It was a bit disappointing that no analyst asked, nor did Dirk volunteer, anything about BD on the recent CC. Especially in context of (the admittedly much simpler) llano sampling, the silence around BD was unfortunate.

Different circumstances back in the day of Barcelona demo(first native QC x86 chip,first AMD's QC chip,new uarchitecture,unnoticed erratum at the time of demo,marketing mistake etc.). There are many reasons why they shouldn't have demoed the chip back then the way they did but it's all the past tense now. They sure won't rush ahead of themselves this time and do the same thing,will they? Even more so when you consider what radical changes to the design AMD made(Design was actually 6+ years in development by now,so better believe it is where they want it to be perf. wise).

[terrace215]

Well, I predict that once they have even minimally functional silicon back, you'll hear about it in the next earnings CC, if not before.

[informal]

They had more than minimally functional Bobcat for a while now and you've heard it just a few days ago.And bobcat is not as big (in every possible sense of the word) as BD will be.

[qcmadness]

I feel that AM3 and it's dual channel memory controller might make Bulldozer a bit memory starved.
But I do hope that AMD finally did something about the lousy IMC in the Phenoms. They simply can't use the bandwidth of DDR3. But that alone isn't good enough.
Benchmarks has showed us that higher IMC clock boosts performance alot, and an IMC at core speed would make even the Phenom II close to nehalem in many aspects.

A triple channel IMC which isn't broken as in Phenoms would be great. But the fact that AMD choose AM3 could be bad news about memory performance, and thereby lower overall performance.

The problem is the design of L3 cache.

Since L3 cache is slower than dual-channel DDR-3, memory bandwidth is limited to L3 cache speed.

[zir_blazer]

The problem is the design of L3 cache.

Since L3 cache is slower than dual-channel DDR-3, memory bandwidth is limited to L3 cache speed.

Then, what about Propus? If the Cache L3 is making a bandwidth bottleneck compared to direct RAM access, then there should be at least a few benchmarks where Propus should perform slighty better than a Deneb at the same settings (Processor Frequency, Cache L3/IMC Frequency, RAM Frequency), specifically intensive memory bandwidth applications where such a limitation could be show. Applications more sensible to memory latency should perform better with Cache L3.

[informal]

The problem is the design of L3 cache.

Since L3 cache is slower than dual-channel DDR-3, memory bandwidth is limited to L3 cache speed.

Are you sure L3 in Deneb is slower than DC DDR3 ? That doesn't seem right. The L3 is in Deneb and Agena has a lot lower latency than any possible DDR3 DC configuration you can think of(think ~7ns for the L3 Vs 45ns in the bet case for OCed DDR3 DC on crack...). BW is another matter,the cores does not need that much bandwidth to begin with. Maybe with 8 BD cores we might see a limitation when all the cores are loaded in some mem. BW limited application.

[zir_blazer]

Are you sure L3 in Deneb is slower than DC DDR3 ? That doesn't seem right. The L3 is in Deneb and Agena has a lot lower latency than any possible DDR3 DC configuration you can think of(think ~7ns for the L3 Vs 45ns in the bet case for OCed DDR3 DC on crack...). BW is another matter,the cores does not need that much bandwidth to begin with. Maybe with 8 BD cores we might see a limitation when all the cores are loaded in some mem. BW limited application.

If anything, that statement could be easily verified by comparing Propus vs Deneb scaling at the same settings.
I think that he is talking about the fact that as Deneb Cores and Cache L3/IMC scales their Frequencies independently, by just overclocking the Cores you are demanding more bandwidth (As you can process more data) yet the Cache L3/IMC will still give you exactly the same. That is why a Propus vs Deneb comparision would be interesing to see if the Cache L3 is working as a bottleneck (Propus performing better in some instances), or if the K10 is such sensitive to memory latency that by making the Cache L3 work faster (So, reducing access latency) may have higher than expected results.

[Helmore]

i was talking about the consumer boards, i know servers had 8 dimms for a LONG time now.

will consumer boards be 4 channel and 4 dimm?

Not in 2011 AFAIK, Zambezi (consumer version of Bulldozer) will launch on AM3.

[Manicdan]

Not in 2011 AFAIK, Zambezi (consumer version of Bulldozer) will launch on AM3.

sorry but that confuses me, will BD for consumers on the newer platform support quad channel at all? i know AM3 we have now wont, but AM3+ maybe?

[hyc]

sorry but that confuses me, will BD for consumers on the newer platform support quad channel at all? i know AM3 we have now wont, but AM3+ maybe?

When you figure out how to add 2 more memory channels while only using 941 pins total, be sure to let the rest of us know.

[snoro]

nah quad channel is for server parts on socket g34.

[Helmore]

When you figure out how to add 2 more memory channels while only using 941 pins total, be sure to let the rest of us know.

Nah, if you figure it out than only tell it to me. I would love to get rich fast .

There will not be a newer platform for BD, BD will make use of what's on the market right now. I'm not a 100% sure about complete backward compatibility, but BD will make use of socket AM3. 2 memory channels only in other words.

They might release a newer socket in the more distant future, one with more memory channels and aimed for consumers. Actually, I'm 100% sure they will launch a new socket in the future, but I'm not sure whether that will be 2012, 2013, 2014 or 2015 .

[zir_blazer]

They might release a newer socket in the more distant future, one with more memory channels and aimed for consumers. Actually, I'm 100% sure they will launch a new socket in the future, but I'm not sure whether that will be 2012, 2013, 2014 or 2015 .

Did you missed out Llano or my other Posts? It should arrive earlier than Bulldozer, and bring a new Socket. And later than that a standalone Bulldozer would be released for Socket AM3. That is where things start to get ugly.

[Manicdan]

ok so because AM2 is duel channel, we had to make AM3 duel channel, and now AM3+ is also going to only be duel channel, thats pretty sucky.

i understand backwords compatible is nice and all, but BD being limited because of the socket used by athlon x2s sounds like its going to hurt more than help. those 2 extra channels could be 5-10% more IPC

i hope they split BD across 2 sockets, current and quad channel, let us decide if we want a 300$ cpu put into a 2 year old motherboard, or buy a new mobo and cpu at the same time for that extra perf

[Helmore]

Did you missed out Llano or my other Posts? It should arrive earlier than Bulldozer, and bring a new Socket. And later than that a standalone Bulldozer would be released for Socket AM3. That is where things start to get ugly.

Oh that's true, but I don't think that Llano will be of much importance to us, not on the desktop at least. It would be useful as a nice HTPC though, but for us it's mainly interesting for laptops.

ok so because AM2 is duel channel, we had to make AM3 duel channel, and now AM3+ is also going to only be duel channel, thats pretty sucky.

i understand backwords compatible is nice and all, but BD being limited because of the socket used by athlon x2s sounds like its going to hurt more than help. those 2 extra channels could be 5-10% more IPC

i hope they split BD across 2 sockets, current and quad channel, let us decide if we want a 300$ cpu put into a 2 year old motherboard, or buy a new mobo and cpu at the same time for that extra perf

How can we know what kind of performance impact it will have before Bulldozer is even launched? It seems to be a bit early to start drawing conclusions about the impact of either 2 or more memory channels. Have you seen the massive performance difference between Bloomfield and Lynnfield? Me neither, there was hardly any difference.
One more thing, many here are talking about IPC but you should be talking about performance as a whole. Pentium 4 may have had lousy IPC, but nobody would have complained about that if it did reach the 10 GHz mark in a 95 Watt TDP. It's about the actual performance you get for your money in a given power budget (and die size, but that only matters to AMD).

[zir_blazer]

Oh that's true, but I don't think that Llano will be of much importance to us, not on the desktop at least. It would be useful as a nice HTPC though, but for us it's mainly interesting for laptops.

Nope.

If mainstream uses a K10 based Fusion (Llano), you are going to be missing Bulldozer in that market segment/socket. The market segmentation that AMD will do is basically what Intel did with Bloomfield at high end (LGA 1366) and Lynnfield for mainstream (LGA 1156), with the exception that AMD had a real reason for having a new Socket. AMD way to do this is to launch a new Desktop Socket for low end and mainstream for Fusion and leaving existing Socket AM3 (Well, a compatible revision for it) to Bulldozer.
From a performance standpoint, Lynnfield and Bloomfield didn't had any major differences (If at all), and the available products in each Socket were similar. This was until Intel released Clarkdale aiming at low end in LGA 1156, then Gulftown aiming at ultra high end in LGA 1366, that things become much more differenciated. However, in AMD, that differenciation bewthem Fusion K10 and Bulldozer could be even higher and you know about it beforehand.

Basically, current Socket AM3 users will have a happy upgrade patch to Bulldozer when it is launched, but people that starts their build from a Llano (That possibily arrives earlier than Bulldozer) would be unable to upgrade to it without changing the platform for an earlier one. Until AMD decides to do a Fusion based Bulldozer, but so far we don't know.

[qcmadness]

Are you sure L3 in Deneb is slower than DC DDR3 ? That doesn't seem right. The L3 is in Deneb and Agena has a lot lower latency than any possible DDR3 DC configuration you can think of(think ~7ns for the L3 Vs 45ns in the bet case for OCed DDR3 DC on crack...). BW is another matter,the cores does not need that much bandwidth to begin with. Maybe with 8 BD cores we might see a limitation when all the cores are loaded in some mem. BW limited application.

I don't have the DDR-3 platform right now, but if you use Everest Memory test, you can get about 10GB/s for L3 cache on Deneb.

If anything, that statement could be easily verified by comparing Propus vs Deneb scaling at the same settings.
I think that he is talking about the fact that as Deneb Cores and Cache L3/IMC scales their Frequencies independently, by just overclocking the Cores you are demanding more bandwidth (As you can process more data) yet the Cache L3/IMC will still give you exactly the same. That is why a Propus vs Deneb comparision would be interesing to see if the Cache L3 is working as a bottleneck (Propus performing better in some instances), or if the K10 is such sensitive to memory latency that by making the Cache L3 work faster (So, reducing access latency) may have higher than expected results.

It would be the design of the L3 / IMC.

In K8 architecture, IMC directly communicates with L2 cache in each core.
The simple illustration is the CnQ-throttled CPUs have lower memory speed.

In K10 architecture, IMC communicates with L3 cache (or NB?) and the bandwidth is limited to NB frequency.

[Chumbucket843]

the concept that ILP is what is going to give bulldozer its advantage is wrong. ILP has been mined out, you will be wasting transistors trying to improve it. its perf/mm2 and memory bandwidth.
http://www.bloobble.com/broadband-pr...ns?itemid=2763
see slide 6.

[qcmadness]

ok so because AM2 is duel channel, we had to make AM3 duel channel, and now AM3+ is also going to only be duel channel, thats pretty sucky.

i understand backwords compatible is nice and all, but BD being limited because of the socket used by athlon x2s sounds like its going to hurt more than help. those 2 extra channels could be 5-10% more IPC

i hope they split BD across 2 sockets, current and quad channel, let us decide if we want a 300$ cpu put into a 2 year old motherboard, or buy a new mobo and cpu at the same time for that extra perf

Even you put 6 memory channels to 1 CPU, the performance is still similar to 2-channel ones.

You even may not notice when your CPU is working in single-channel mode at all.

[BeepBeep2]

ok so because AM2 is duel channel, we had to make AM3 duel channel, and now AM3+ is also going to only be duel channel, thats pretty sucky.

i understand backwords compatible is nice and all, but BD being limited because of the socket used by athlon x2s sounds like its going to hurt more than help. those 2 extra channels could be 5-10% more IPC

i hope they split BD across 2 sockets, current and quad channel, let us decide if we want a 300$ cpu put into a 2 year old motherboard, or buy a new mobo and cpu at the same time for that extra perf

They need to focus on frequency and compatibility before they focus on more channels.

Doing 2100-2200 Mhz on am AMD system in the future would be like heaven for us...we are limited to ~1800-1880

[Chumbucket843]

I don't have the DDR-3 platform right now, but if you use Everest Memory test, you can get about 10GB/s for L3 cache on Deneb.



It would be the design of the L3 / IMC.

In K8 architecture, IMC directly communicates with L2 cache in each core.
The simple illustration is the CnQ-throttled CPUs have lower memory speed.

In K10 architecture, IMC communicates with L3 cache (or NB?) and the bandwidth is limited to NB frequency.

http://www.xbitlabs.com/articles/cpu...0_8.html#sect4
it never touches the memory controller, its been that way for like 15 years! iirc dual independent buses were on pentium 2. a memory controller is basically like a server/client network that is used for DRAM only. it runs at the same frequency as the DRAM clockspeed. the whole idea of L3 cache is so cores can communicate with out touching mem controller or main memory. as far as bandwidth goes it should be around 50GB/s with significantly lower latency.

[qcmadness]

http://www.xbitlabs.com/articles/cpu...0_8.html#sect4
it never touches the memory controller, its been that way for like 15 years! iirc dual independent buses were on pentium 2. a memory controller is basically like a server/client network that is used for DRAM only. it runs at the same frequency as the DRAM clockspeed. the whole idea of L3 cache is so cores can communicate with out touching mem controller or main memory. as far as bandwidth goes it should be around 50GB/s with significantly lower latency.

but then it could not explain the lower DDR-2 memory bandwidth when comparing K10 with K8?

[informal]

but then it could not explain the lower DDR-2 memory bandwidth when comparing K10 with K8?

I think it's the problem of measuring the BW on 10h systems due to design change(unganged/ganged is a new thing in 10h Vs the old K8). I remember very well that first sisoft sandra results very very poor on 10h simply because the app was not programmed for the new IMC organization 10h had when it showed up.
What matters is memory latency and L3 helps a lot(as any cache does since it is heaps faster than any regular DDR memory out there).
Now BD will have much improved memory controller and will support even higher DDR3 speeds (1600+). That should be enough even for 8 cores.

[xlink]

BD will not support DDR2.

looks like I won't be going for AMD the gen unless BD is truly exceptional.

shame, I was hoping for a drop in replacement. ohh well.

[JF-AMD]

looks like I won't be going for AMD the gen unless BD is truly exceptional.

shame, I was hoping for a drop in replacement. ohh well.

Let me rephrase that:

NOTHING IN 2011 WILL BE SUPPORTING DDR2.

Sure, that is an extreme statement, but let's be realistic.

Can you replace a DDR1 processor today with anything faster? Is it worth it?